View MK68564_5615560.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MK68564 january 1989 serial input output . compatible with mk68000 cpu . compatible with mk68000 series dma's . two independent full-duplex chan- nels . two independent baud-rate gener- ators - crystal oscillator input - single-phase ttl clock input . directly addressable registers (all control registers are read/write) . data rate in synchronous or asyn- chronous modes - 0-1.25m bits/second with 5.0mhz system clock rate . self-test capability . receive data registers are quadru- ply buffered ; transmit registers are doubly buffered . daisy-chain priority interrupt logic provides automatic interrupt vecto- ring without external logic . modem status can be monitored - separate modem controls for each channel . asynchronous features - 5, 6, 7, or 8 bits/character - 1, 1 1/2 , or 2 stop bits - even, odd, or no parity - x1, x16, x32, and x64 clock modes - break generation and detection - parity, overrun, and framing error detection . byte synchronous features - internal or external character synchronization - one or two sync characters in separate regis- ters - automatic sync character insertion - cdc-16 or crc-ccitt block check genera- tion and checking . bit synchronous features - abort sequence generation and detection - automatic zero insertion and deletion - automatic flag insertion between messages - address field recognition - i-field residue handling - valid receive messages protected from over- run - crc-16 or crc-ccitt block check genera- tion and checking description the MK68564 sio (serial input output) is a dual- channel, multi-function peripheral circuit, designed to satisfy a wide variety of serial data communica- tions requirements in microcomputer systems. its basic function is a serial-to-parallel, parallel-to-serial converter/controller ; however within that role, it is systems software configurable so that its "persona- lity" may be optimized for any given serial data communications application. the MK68564 is capable of handling asynchronous protocols, synchronous byte-oriented protocols (such as ibm bisync), and synchronous bit-oriented protocols (such as hdlc and ibm sdlc). this ver- satile device can also be used to support virtually any serial protocol for applications other than data communications (cassette or floppy disk interface, for example). the MK68564 can generate and check crc codes in any synchronous mode and may be programmed to check data integrity in various modes. the device also has facilities for modem controls in each chan- nel. in applications where these controls are not needed, the modem controls may be used for gene- ral-purpose i/o. pdip48 (plastic package) plcc52 (chip carrier) 1 1/46
sio pin description gnd : ground v cc : + 5 volts ( 5%) cs : chip select (input, active low). cs is used to select the MK68564 sio for accesses to the internal registers. cs and iack must not be asserted at the same time. r/w : read/write (input). r/w is the signal from the bus master, indicating wether the current bus cycle is a read (high) or write (low) cycle. dtack : data transfer acknowledge (output, active low, three stateable). dtack is used to signal the bus master that data is ready or that data has been accepted by the MK68564 sio. a1-a5 : address bus (inputs). the address bus is used to select one of the internal registers during a read or write cycle. d0-d7 data bus (bidirectional, threee-stateable). the data bus is used to transfer data to or from the internal registers during a read or write cycle. it is also used to pass a vector during an interrupt acknowledge cycle. clk : clock (input). this input is used to provide the internal timing for the MK68564 sio. reset : device reset (input, active low). reset disables both receivers and transmitters, forces txda and txdb to a marking condition, forces the modem controls high and disables all interrupts. with the exception of the status registers, data registers, and the vector register, all internal registers are cleared. the vector register is reset to "0fh". intr : interrupt request (output, active low, open drain). intr is asserted when the MK68564 sio is requesting an interrupt. intr is negated during an interrupt acknowledge cycle or by clearing the pending interrupt(s) through software. iack : interrupt acknowledge (input, active low). iack is used to signal the MK68564 sio that the cpu is acknowledging an interrupt. cs and iack must not be asserted at the same time. iei : interrupt enable in (input, active low). iei is used to signal the MK68564 sio that no higher priority device is requesting interrupt service. ieo : interrupt enable out (output, active low). ieo is used to signal lower priority peripherals that neither the MK68564 sio nor another higher priority peripheral is requesting interrupt service. xtal1, xtal2 : baud rate generator inputs. a crystal may be connected between xtal1 and xtal2, or xtal1 may be driven with a ttl level clock. when using a crystal, external capacitors must be connectd. when driving xtal1 with a ttl level clock, xtal2 must be allowed to float. rxrdya , rxrdyb : receiver ready (outputs, active low). programmable dma output for the receiver. the rxrdy pins pulse low when a character is available in the receive buffer. txrdya , txrdyb : transmitter ready (outputs, active low). programmable dma output for the transmitter. the txrdy pins pulse low when the transmit buffer is empty. ctsa , ctsb : clear to send (inputs, active low). if tx auto enables is selected, these inputs enable the transmitter of their respective channels. if tx auto enables is not selected, these inputs may be used as general purpose input pins. the inputs are scmit-trigger buffered to allow slow rise-time input signals. dcda , dcdb : data carrier detect (inputs, active low). if rx auto enables is selected, these inputs enable the receiver of their respective channels. if rx auto enables is not selected, these inputs may be used as general purpose input pins. the inputs are schmit-trigger buffered to allow slow rise-time input signals. rxda, rxdb : receive data (inputs, active high). serial data input to the receiver. txda, txdb : transmit data (outputs, active high). serial data output of the transmitter. MK68564 2/46
sio pin description (continued) rxca, rxcb : receiver clocks (input/output). programmable pin, receive clock input, or baud rate generator output. the inputs are schmit-trigger buffered to allow slow rise-time input signals. txca, txcb : transmitter clocks (input/output). programmable pin, transmit clock input, or baud rate generator output. the inputs are schmit-trigger buffered to allow slow rise-time input signals. rtsa, rtsb : request to send (outputs, active low). these outputs follow the inverted state programmed into the rts bit. when the rts bit is reset in the asynchronous mode, the output will not change until the character in the transmitter is completely shifted out. these pins may be used as general purpose outputs. dtra , dtrb : data terminal ready (outputs, active low). these outputs follow the inverted state programmed into the dtr bit. these pins may also be used as general purpose outputs. synca , syncb : synchronization (input/output, active low). the sync pin is an output when monosync, bisync, or sdlc mode is programmed. it is asserted when a sync/flag character is detected by the receiver. the sync pin is a general purpose input in the asynchronous mode and an input to the receiver in the external sync mode. figure 1a : dual in line pin configuration. figure 1b : chip carrier pin configuration. MK68564 3/46
sio system interface introduction the MK68564 sio is designed for simple and effi- cient interface to a mk68000 cpu system. all data transfers between the sio and the cpu are asyn- chronous to the system clock. the sio system timing is derived from the chip select input ( cs) du- ring normal read and write sequences, and from the interrupt acknowledge input ( iack) during an ex- ception processing sequence. cs is a function of address decode and (normally) lower data strobe ( lds). iack is a function of the interrupt level on ad- dress lines a1, a2, and a3, an interrupt acknow- ledge function code (fc0-fc2), and lds. note : cs and iack can never be asserted at the same time. note : unused inputs should be pulled up or down, but never left floating. read sequence the sio will begin a read cycle if, on the falling edge of cs, the read-write (r/ w) pin is high. the sio will respond by decoding the address bus (a1-a5) for the register selected, by placing the contents of that register on the data bus pins (d0-d7), and by driving the data transfer acknowledge ( dtack) pin low. if the register selected is not implemented on the sio, the data bus pins will be driven high, and then dtack will be asserted. when the cpu has acqui- red the data, the cs signal is driven high, at which time the sio will drive dtack high and then three- state dtack and d0-d7. write sequence the sio will begin a write cycle if, on the falling edge of cs, the r/w pin is low. the sio will respond by latching the data bus, by decoding the address bus for the register selected, by loading the register with the contents of the data bus, and by driving dtack low. when the cpu has finished the cycle, the cs input is driven high. at this time, the sio will drive dtack high and will then three-state dtack. if the register selected is not implemented on the sio, the normal write sequence will proceed, but the data bus contents will not be stored. interrupt sequence the sio is designed to operate as an independent, interrupting peripheral, or, when interconnected with other components, an interrupt priority daisy chain can be formed. independent operation . independent operation requires that the interrupt enable in pin ( iei) be connected to ground. the sio starts the interrupt sequence by driving the interrupt request pin ( intr) low. the cpu responds to the interrupt by starting an interrupt acknowledge cycle, in which the sio iack pin is driven low. the highest priority interrupt request in the sio, at the time iack goes low, places its vector on the data bus pins. the sio releases the intr pin and drives dtack low. when the cpu has acquired the vector, the iack signal is driven high. the sio responds by driving dtack to a high level and then three-stating dtack and d0-d7. if more than one interrupt request is pending at the start of an interrupt acknowledge sequence, the sio will drive the intr pin low following the completion of the interrupt acknowledge cycle. this sequence will continue until all pending interrupts are cleared. if the sio is not requesting an interrupt when iack goes low, the sio will not respond to the iack signal ; dtack and the data bus will remain three-stated. daisy chain operation . the interrupt priority chain is formed by connecting the interrupt enable out pin ( ieo) of a higher priority part to iei of the next lower priority part. the highest priority part in the chain should have iei tied to ground. the daisy chaining capability (figures 2 and 3) requires that all parts in a chain have a common iack signal. when the common iack goes low, all parts freeze and priori- tize interrupts in parallel. then priority is passed down the chain, via iei and ieo, until a part which has a pending interrupt, once iei goes low, passes a vector, does not propagate ieo, and generates dtack. the state of the iei pin does not affect the sio in- terrupt control logic. the sio can generate an inter- rupt request any time its interrupts are enabled. the ieo pin is normally high ; it will only go low during an iack cycle if iei is low and no interrupt is pending in the sio. the ieo pin will be forced high whenever iack or iei goes high. MK68564 4/46
figure 2 : conceptual circuit of the MK68564 sio daisy chaining logic. figure 3 : daisy chaining. v000376 v000377 figure 4 : dma interface timing. v000378 MK68564 5/46
dma interface the sio is designed to interface to the 68000 family dma's as a 68000 compatible device, using the cy- cle steal mode. the sio provides four outputs ( txrdya, rxrdya, txrdyb, rxrdyb) for re- questing service from the dma. the sio issues a re- quest for service by pulsing the rdy pin low for three clock (clk) cycles (see figure 4). txrdy (when en- abled) will be active when the transmit buffer be- comes empty. rxrdy (when enabled) will be active when a character is available in the receive buffer. if receive interrupt on first character only is en- abled during a dma operation and a special receive condition is detected, the rxrdy pin will not be- come active. instead, a special receive condition in- terrupt will be generated by the channel. reset there are two ways of resetting the sio : an indivi- dual, programmable channel reset and an external hardware reset. the individual channel reset is generated by writing "18h" to the command register for the channel se- lected. all outputs associated with the channel are reset high, txc and rxc are inputs, sync is an out- put, and txd is forced marking. all r/w registers for the channel are reset to "00h", except the vector re- gister and the data register, which are not affected. read only status register 1 is reset to "01h" (all sent set). break/abort, interrupt pending, and rx char- acter available bits in read only status register 0 are reset ; underrun/eom, hunt/sync, and tx buffer empty are set ; cts and dcd bits are set to the in- verted state of their respective input pins. any inter- rupts pending for the channel are reset (any pending interrupts in the other channel will not be affected). an external hardware reset occurs when the reset pin is driven low for at least one clock (clk) cycle. both channels are reset as listed above, and the vector register is reset to "0fh". architecture the MK68564 sio contains two independent, full- duplex channels. each channel contains a transmit- ter, receiver, modem control logic, interrupt control logic, a baud rate generator, ten read/write regis- ters, and two read only status registers. each chan- nel can communicate with the bus master using pol- ling, interrupts, dma, or any combination of these three techniques. each channel also has the ability to connect the transmitter output into the receiver wi- thout disturbing any external hardware. register set . the register set is the heart of each channel. a channel is configured for different communication protocols and interface options by programming the registers. table 1 lists all the re- gisters available in the sio and their addresses. data register . the data register is composed of two separate registers : a write only register, which is the transmit buffer, and a read only register, which is the receive buffer. the receive buffer is also the top register of a three register stack called the receive data fifo. vector register . the vector register is different from the other 24 registers, because it may be ac- cessed through either channel a or channel b du- ring a r/ w cycle. during an interrupt acknowledge cycle, the contents of the vector register are pas- sed to the cpu to be used as a pointer to an interrupt service routine. if the status affects vector bit is low in the interrupt control register, any data written to the vector register will be returned unmodified du- ring a read cycle or an iack cycle. if the status af- fects vector bit is high, the lower three bits of the vector returned during a read or iack cycle are mo- dified to reflect the highest priority interrupt pending in the sio at that time. the upper five bits written to the vector register are unaffected. after a hardware reset only, this register contains a "0fh" value, which is the mk68000's uninitialized interrupt vector assignment. MK68564 6/46
figure 5 : register bit functions. MK68564 7/46
sio internal registers the MK68564 sio has 25 internal registers. each channel has ten r/w registers and two read only registers associated with it. the vector register may be accessed through either channel. address access 54321 abbreviation channel register name read/ write read only 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 cmdreg modectl intctl sync 1 sync 2 rcvctl xmtctl stat 0 stat 1 datarg tcreg brgctl vectrg cmdreg modectl intctl sync 1 sync 2 rcvctl xmtctl stat 0 stat 1 datarg tcreg brgctl vectrg a a a a a a a a a a a a a/b a a a b b b b b b b b b b b b a/b b b b command register x mode control register x interrupt control register x sync word register 1 x sync word register 2 x receiver control register x transmitter control register x status register 0 x status register 1 x data register x time constant register x baud rate generator control reg x interrupt vector register (note 2) x (note 1) x (note 1) x (note 1) x command register x mode control register x interrupt control register x sync word register 1 x sync word register 2 x receiver control register x transmitter control register x status register 0 x status register 1 x data register x time constant register x baud rate generator control reg x interrupt vector register (note 2) x (note 1) x (note 1) x (note 1) x notes : 1. not used, read as "ffh". 2. only one vector register, accessible through either channel. table 1 : register map . MK68564 8/46
figure 6 : transmit and receive data paths. v000379 MK68564 9/46
data path the transmit and receive data paths for each chan- nel are shown in figure 6. the receiver has three 8-bit buffer registers in a fifo arrangement (to pro- vide a 3-byte delay) in addition to the 8-bit receive shift register. this arrangement creates additional time for the cpu to service an interrupt at the begin- ning of a block of high-speed data. the receiver er- ror fifo stores parity and framing errors and other types of status information for each of the three bytes in the receive data fifo. the receive error fi- fo is loaded at the same time as the receive data fifo. the contents of the receive error are read through the upper four bits in status register 1. incoming data is routed through one of several paths, depending on the mode and character length. in the asynchronous modes, serial data is entered into the 3-bit buffer, if it has a character length of se- ven or eight bits, or the data is entered into the 8-bit receive shift register, if it has a length of five or six bits. in the synchronous mode, the data path is determi- ned by the phase of the receive process currently in operation. a synchronous receive operation be- gins with the receiver in the hunt phase, during which time the receiver searches the incoming data stream for a bit pattern that matches the prepro- grammed sync characters (or flags in the sdlc mode). if the device is programmed for monosync hunt, a match is made with a single sync character stored in sync word register 2. in bisync hunt, a match is made with the dual sync characters stored in sync word registers 1 and 2. in either case, the incoming data passes through the receive sync re- gister and is compared against the programmed sync characters in sync word registers 1 and 2. in the monosync mode, a match between the sync character programmed into sync word register 2 and the character assembled in the receive sync re- gister establishes synchronization. in the bysync mode, incoming data is shifted to the receive shift register, while the next eight bits of the message are assembled in the receive sync regis- ter. the match between the assembled character in the sync register and the programmed character in sync word register 2, and between the character in the shift register and the programmed character in sync word register 1 establishes synchroniza- tion. once synchronization is established, incoming data bypasses the receive sync register and directly enters the 3-bit buffer. in the sdlc mode, all incoming data passes through the receive sync register, which continuous- ly monitors the receive data stream and performs zero deletion when indicated. upon receiving five contiguous ones, the sixth bit is inspected. if the sixth bit is a 0, it is deleted from the data stream. if the sixth bit is a 1, the seventh bit is inspected. if the seventh bit is a 0, a flag sequence has been recei- ved ; if the seventh bit is a 1, an abort sequence has been received. the reformatted data from the receive sync register enters the 3-bit buffer and is transferred to the re- ceive shift register. note that the sdlc receive ope- ration also begins in the hunt phase, during which time the sio tries to match the assembled character in the receive sync register with the flag pattern in sync word register 2. once the first flag character is recognized, all subsequent data is routed through the path described above, regardless of character length. although the same crc checker is used for both sdlc and synchronous data, the path taken for each mode is different. in bisync protocol, the byte- oriented operation requires that the cpu decide whether or not to include the data character in the crc calculation. to allow the cpu ample time to make this decision, the sio provides an 8-bit delay before the data enters the crc checker. in the sdlc mode, no delay is provided, since crc is cal- culated on all data between the opening and closing flags. the transmitter has an 8-bit transmit data register, which is loaded from the internal bus, and a 20-bit transmit shift register, which can be loaded from sync word register 1, sync word register 2, and the transmit data register. sync word registers 1 and 2 contain sync characters in the monosync, bi- sync, or external sync modes, or address field (one character long) and flag, respectively, in the sdlc mode. during synchronous modes, information contained in sync word registers 1 and 2 is loaded into the transmit shift register at the beginning of the message and, as a time filler, in the middle of the message if a transmit underrun condition occurs. in sdlc mode, the flags are loaded into the transmit shift register at the beginning and end of the mes- sage. asynchronous data in the transmit shift register is formatted with start and stop bits, and it is shifted out to the transmit multiplexer at the selected clock rate. synchronous (monosync, bisync, or external sync) data is shifted out to the transmit multiplexer and al- so the crc generator at the x1 clock rate. sdlc/hdlc data is shifted out through the zero in- sertion logic, which is disabled while flags are being sent. for all other fields (address, control, and frame check), a 0 is inserted following five contiguous ones MK68564 10/46
in the data stream. note that the crc generator re- sult (frame check) for sdlc data is also routed through the zero insertion logic. i/o capabilities the sio offers the choice of polling, interrupt (vec- tored or non-vectored), and dma transfer modes to transfer data, status, and control information to and from the cpu or other bus master. polling . the polled mode avoids interrupts. status registers 0 and 1 are updated at appropriate times for each function being performed (for example, crc error status valid at the end of the message). all the interrupt modes of the sio must be disabled to operate the device in a polled environ- ment. while in its polling sequence, the cpu examines the status contained in status register 0 for each chan- nel. the state of the status bits in status register 0 serves as an acknowledge to the poll inquiry. status bits d0 and d2 indicate that a receive or transmit da- ta transfer is needed. the rest of the status bits in status register 0 indicate special status conditions. the receiver error condition bits in status register 1 do not have to be read until the rx character avai- lable status bit in status register 0 is set to a one. interrupts . the sio offers an elaborate interrupt scheme to provide fast interrupt response in real- time applications. the interrupt vector points to an interrupt service routine in the memory. to service operations in both channels and to eliminate the ne- cessity of writing a status analysis routine (as requi- red for a polling scheme), the sio can modify the in- terrupt vector so it points to one of eight interrupt ser- vice routines. this is done under program control by setting the status affects vector bit in the interrupt control register of channel a or channel b, to a one. when this bit is set, the interrupt vector is modified according to the assigned priority of the various in- terrupting conditions. note : if the status affects vector bit is set in either channel, the vector is modified for both channels. this is the only control bit that operates in this man- ner in the sio. transmit interrupts, receive interrupts, and exter- nal/status interrupts are the sources of interrupts. each interrupt source is enabled under program control with channel a having a higher priority than channel b, and with receiver, transmitter, and ex- ternal/status interrupts prioritized in that order within each channel. when the transmit interrupt is en- abled, the cpu is interrupted by the transmit buffer becoming empty. this implies that the transmitter must have had a data character written into it so t can become empty. when enabled, the receiver can interrupt the cpu in one of three ways : interrupt on first character only interrupt on all receive characters interrupt on a special receive condition. interrupt on first character only .this mode is normally used to start a software polling loop or a dma transfer routine using the rxrdy pin. in this mode, the sio generates an interrupt on the first character received after this mode is selected and, thereafter, only generates an interrupt if a special receive condition occurs. the special receive conditions that can cause an interrupt in this mode are : rx overrun error, framing error (in asynchro- nous modes), and end of frame (in sdlc mode). this mode is reinitialized by the enable interrupt on next rx character command. if a special receive condition interrupt occurs in this interrupt mode, the data with the special condition is held in the receive data fifo until an error reset command is issued. interrupt on all receive characters . in this mode, an interrupt is generated whenever the receive data fifo contains a character or a special receive condition occurs. the special receive conditions that can cause an interrupt in this mode are : rx o- verrun error, framing error (in asynchronous modes), end of frame (in sdlc mode), and parity error (if selected). interrupt on a special receive condition . the special receive condition interrupt is not, as such, a separate interrupt mode. before a special re- ceive condition can cause an interrupt, either the in- terrupt on first character only or interrupt on all receive characters mode must be selected. the special receive condition interrupt will modify the receive interrupt vector if status affects vector is en- abled. the special receive condition status is dis- played in the upper four bits of status register 1. two of the conditions causing a special receive in- terrupt are latched when they occur ; they are : parity error and rx overrun error. these status bits may only be reset by an error reset command. when ei- ther of these conditions occur, a read of status re- gister 1 will reflect any errors in the current word in the receive buffer plus any parity or overrun errors since the last error reset command was issued. external/status interrupts . the main function of the external/status interrupt is to monitor the signal transitions of the cts, dcd, and sync pins ; how- ever, an external/status interrupt is also caused by a transmit underrun condition or by the detection of a break (asynchronous mode) or abort (sdlc mode) sequence in the received data stream. when any one of the above conditions occur, the exter- MK68564 11/46
dma transfer the sio provides two output signals per channel for connection to a dma controller ; they are txrdy and rxrdy. the outputs are enabled under soft- ware control by writing to the interrupt control re- gister. both outputs will pulse low for three system clock cycles when their input conditions are active. txrdy will be active when the transmit buffer becomes empty. rxrdy will be active when a char- acter is available in the receive buffer. if a special receive condition occurs when interrupt on first character only mode is selected, a receiver inter- rupt will be generated and rxrdy will not become active. this will automatically inform the cpu of a discrepancy in the data transfer. nal/status logic latches the current state of all five in- put conditions, and generates an interrupt. to reini- tialize the external/status logic to detect another transition, a reset external/status interrupts command must be issued. the break/abort condi- tion allows the sio to generate an interrupt when the break/abort sequence is detected and terminated. this feature facilitates the proper termination of the current message, correct initialization of the next message, and the accurate timing of the break/a- bort condition in external logic. self test when the loop mode bit is set in the command re- gister, the receiver shift clock input pin (rxc) and the receiver data input pin (rxd) are electrically dis- connected from the internal logic. the transmit data output pin (txd ) is connected to the internal receiver data logic, and the transmit shift clock pin (txc) is connected to the internal receiver shift clock logic. all other features of the sio are unaffected. baud rate generators each channel in the sio contains a programmable baud rate generator (brg). each brg consists of an 8-bit time constant register, an 8-bit down coun- ter, a control register, and a flip-flop on the output to provide a square wave signal out. in addition to the flip-flop on the output, there is also a flip-flop on the input clock ; therefore, the maximum output frequen- cy of the brg is one-forth of the input clock frequen- cy. this maximum output frequency occurs when divide by four mode is selected, and the time constant register is loaded with the minimum count of "01h". the equation to determine the output fre- quency is : output = input frequency frequency (divide by selected) x (time constant value in decimal) figure 7 : interrupt structure. v000380 MK68564 12/46
for example, when the time constant register is loa- ded with "01h" and divide by four is selected, one output clock will occur for every four input clocks. if the time constant value loaded is "00h" (256 deci- mal) instead of "01h" and divide by 64 is selected, one output clock will occur for every 16384 input clocks. note that the minimum count value is "01h" (1 decimal), and the maximum count value is "00h" (256 decimal). the output of the baud rate generator may be pro- grammed to drive the transmitter (brg output on txc), the receiver (brg output on rxc), both (brg output on txc and rxc), or neither ( txc and rxc are inputs). after a reset, the baud rate generator is disabled, divide by four is selected, and txc and rxc are inputs. the baud rate generator should be disabled before the cpu writes to the time constant register. this is necessary because no attempt was made to syn- chronize the loading of a new time constant with the clock used to drive the brg. figure 8 indicates the external components needed to connect a crystal oscillator to the sio xtal in- puts. the allowed crystal parameters are also listed. for a 3.6864mhz input signal to the baud rate ge- nerator, the time constants, listed in table 2, are loa- ded to obtain the desired baud rates (in x1 clock mode). figure 8 : sio external oscillator components. table 2 : time-constant values. rate time constant divide by error 19200 9600 7200 4800 3600 2400 2000 1800 1200 600 300 48 96 128 192 256 24 29 32 48 96 192 4 4 4 4 4 64 64 64 64 64 64 69 % crystal parameters : parallel resonance, fundamental mode at cut rs a 150 w (fr = 2.8 - 5.0mhz) rs a 300 w (fr = 2.0 - 2.7mhz) ci = 18pf ; cm = 0.02pf ; ch = 5pf ; lm = 96mhz fr (typ) = 2.457mhz asynchronous operation introduction many types of asynchronous operations are perfor- med by the MK68564 sio. figure 9 represents a ty- pical asynchronous message format and some of the options available on the sio. the transmit pro- cess inserts start, stop, and parity bits to a variable data format and supplies a serial data stream to the transmit data output (txd). the receiver takes the data from the receive data input (rxd) and strips away expected start and stop bits at a programmed clock rate. it provides error checking for overrun, pa- rity, and carrier-loss errors, and, if desired, provides interrupts for these conditions. to set up the sio for asynchronous operation, the following registers need to be initialized : mode control register, interrupt control register, recei- ver control register, and transmitter control register. the mode control register must be programmed before the other registers to assure proper operation of the sio. the following registers are used to transfer data or to communicate status between the sio and the cpu or other bus master when operating in asynchronous modes : command register, status register 0, status re- gister 1, data register, and the vector register. MK68564 13/46
figure 9 : asynchronous message format. v000382 the sio provides five i/o lines that may be used for modem control, for external interrupts, or as general purpose i/o. the request to send ( rts) and data terminal ready ( dtr) pins are outputs that follow the inverted state of their respective bits in the transmitter control register. the rts pin can also be used to signal the end of a message in asynchro- nous modes, as explained below in the transmitter section. the data carrier detect ( dcd), clear to send ( cts), and sync pins are inputs to the sio in asynchronous modes. dcd and cts can be u- sed as auto enables to the receiver and transmitter, respectively, or if external/status interrupts are en- abled all three input pins will be monitored for a change of status. if these inputs change for a period of time greater than the minimum specified pulse width, an interrupt will be generated. in the following discussion, all interrupt modes are assumed enabled. asynchronous transmit start of transmission . the sio will start transmit- ting data when the transmit enable bit is set to a one, and a character has been loaded into the trans- mit buffer. if the txauto enables bit is set, the sio will wait for a low on the clear to send input (cts) before starting data transmission. the tx auto en- ables feature allows the programmer to send the first data character of the message to the sio wi- thout waiting for cts to go low. in all cases, the transmit enable bit must be set before transmission can begin. the transitions on the cts pin will gene- rate external/status interrupt requests and also latch up the external/status logic. the external/sta- tus logic should be rearmed by issuing a reset ex- ternal/status interrupts command. transmit characteristics . the sio automatically inserts a start bit, the programmed parity bit (odd, e- ven, or no parity), and the programmed number of stop bits to the data character to be transmitted. the transmitter can transmit from one to eight data bits per character. all characters are transmitted least- significant bit first. when the character length pro- grammed is six or seven bits, the unused bits of the transmit buffer are automatically ignored. when a character length of five bits or less is programmed, the data loaded into the transmit buffer must be for- matted as described in the transmitter control re- gister part of the register description section. serial data is shifted out of the txd pin on the falling edge of the transmit clock ( txc) at a rate equal to 1, 1/16th, 1/32nd, or 1/64th of txc. data transfer . the sio will signal the cpu or other bus master with a transmit interrupt request and set the tx buffer empty bit in status register 0, every time the contents of the transmit buffer are loaded into the transmit shift register. the interrupt request will be cleared when a new character is loaded into the transmit buffer, or a reset tx interrupt pending command (command 5) is issued. if command 5 is issued, the transmit buffer will have to be loaded be- fore any additional transmit interrupt requests are generated. the tx buffer empty bit is reset when a new character is loaded into the transmit buffer. the all sent bit in status register 1 is used to indi- cate when all data in the shift register has been transmitted, and the transmit buffer is empty. this bit is low, while the transmitter is sending characters, and it will go high one bit time after the transmit clock that clocks out the last stop bit of the character on the txd pin. no interrupts are generated by the all sent bit transitions. the request to send (rts) bit MK68564 14/46
in the transmitter control register may also be u- sed to signal the end of transmission. if this bit is set to a one, its associated output pin (rts) will go low. when this bit is reset to a zero, the rts pin will go high one bit time after the transmit clock that clocks out the last stop bit, only if the transmit buffer is emp- ty. the transmit data output (txd) is held marking (high) after a reset or when the transmitter has no data to send. under program control, the send break command can be issued to hold txd spacing (low) until the command is cleared, even if the transmitter is not enabled. asynchronous receive asynchronous operation begins when the receiver enable bit in the receiver control register is set to a one. if the rx auto enables bit is also set, the data carrier detect ( dcd) input pin must be low as well. the receiver will start assembling a character as soon as a valid start bit is detected, if a clock mode other than x1 is selected. a valid start bit is a high- to-low transition on the receive data input (rxd) with the low time lasting at least one-half bit time. the high-to-low transition starts an internal counter and, at mid-bit time, the counter output is used to sample the input signal to detect if it is still low. when this condition is satisfied, the following data bits are sampled at mid-bit time until the entire char- acter is assembled. the start bit detection logic is then rearmed to detect the next high-to-low trans- ition. if the x1 clock mode is selected, the start bit de- tection logic is disabled, and bit synchronization must be accomplished externally. receive data is sampled on the rising edge of the receiver clock ( rxc). the receiver may be programmed to assemble five to eight data bits, plus a parity bit, into a character. the character is right-justified in the shift register and then transferred to the receive data fifo. all da- ta transfers to the fifo are in eight-bit groups. if the character length assembled is less than eight bits, the receiver inserts ones in the unused bits. if parity is enabled, the parity bit is transferred with the char- acter, unless eight bits per character is program- med, in which case, the parity bit is stripped from the character before transfer. a receiver interrupt request is generated every time a character is shifted to the top of the receive data fifo, if interrupt on all receive characters mode is selected. the rx character available bit in status register 0 is also set to a one every time a character is shifted to the top of the receive data fifo. the rx character available bit is reset to a zero when the receive buffer is read. after a character is received, it is checked for the fol- lowing error conditions : parity error . if parity is enabled, the parity error bit in status register 1 is set to a one whenever the pa- rity bit of the received character does not match the programmed parity. once this bit is set, it remains set (latched), until an error reset command (command 6) is issued. a special receive condi- tion interrupt is generated when this bit is set, if parity is programmed as a special receive condition. framing error . the crc/framing error bit in sta- tus register 1 is set to a one, if the character is as- sembled without a stop bit (a low level detected ins- tead of a stop bit). this bit is set only for the character on which the framing error occurred ; it is updated at every character time. detection of a framing error adds an additional one-half of a bit time to the char- acter time, so the framing error is not interpreted as a new start bit. a special receive condition interrupt is generated when this bit is set.. overrun error . if four or more characters are recei- ved before the cpu (or other bus master) reads the receive buffer, the fourth character assembled will replace the third character in the receive data fifo. if more than four characters have been received, the last character assembled will replace the third char- acter in the data fifo. the character that has been written over is flagged with an overrun error in the error fifo. when this character is shifted to the top of the re- ceive data fifo, the receive overrun error bit in status register 1 is set to a one ; the error bit is lat- ched in the status register, and a special receive condition interrupt is generated. like parity error, this bit can only be reset by an error reset command. break condition . a break character is defined as a start bit, an all zero data word, and a zero in place of the stop bit. when a break character is detected in the receive data stream, the break/abort bit in status register 0 is set to a one, and an exter- nal/status interrupt is requested. this interrupt is then followed by a framing error interrupt request when the crc/framing error bit in status register 1 is set. a reset external/status interrupts command (command 2) should be issued to reini- tialize the break detection interrupt logic. the recei- ver will monitor the data stream input for the termi- nation of the break sequence. when this condition is detected, the break/abort bit will be reset, if MK68564 15/46
command 2 has been issued, and another exter- nal/status interrupt request will be generated. this interrupt should also be handled by issuing command 2 to reinitialize the external/status logic. at the end of the break sequence, a single null char- acter will be left in the receive data fifo. this char- acter should be read and discarded. because parity error and receive overrun error flags are latched, the error status that is read from status register 1 reflects an error in the current word in the receive data fifo, plus any parity or o- verrun errors received since the last error reset command. to keep correspondence between the state of the error fifo and the contents of the re- ceive data fifo, status register 1 should be read before the receive buffer. if the status is read after the data and more than one character is stacked in the data fifo during the read of the receive buffer, the status flags read will be for the next word. keep in mind that when a character is shifted up to the top of the data fifo (the receive buffer), its error flags are shifted into status register 1 .an exception to the normal flow of data through the receive data fifo occurs when the receive inter- rupt on first character only mode is selected. a special receive condition interrupt in this mode holds the error data, and the character itself (even if read from the data fifo) until the error reset command (command 6) is issued. this prevents fur- ther data from becoming available in the receiver, until command 6 is issued, and allows cpu inter- vention on the character with the error even if dma or block transfer techniques are being used. synchronous operation introduction before describing byte-oriented, synchronous transmission and reception, the three types of char- acter synchronization - monosync, bysync, and ex- ternal sync - require some explanation. these modes use the x1 clock for both transmit and re- ceive operations. data is sampled on the rising edge of the receive clock input ( rxc). transmitter data transitions occur on the falling edge of the transmit clock input ( txc). the differences between monosync, bisync, and external sync are in the manner in which initial re- ceive character synchronization is achieved. the mode of operation must be selected before sync characters are loaded, because the registers are u- sed differently in the various modes. figure 10 shows the formats for all three synchronous modes. monosync. in the monosync mode (8-bit sync mode), the transmitter transmits the sync character in sync word register 1. the receiver compares the single sync character with the programmed sync character stored in sync word register 2. a match implies character synchronization and enables data transfer. the sync pin is used as an output in this mode and is active for the part of the receive clock that detects the sync character. bisync. in the bisync mode (16-bit sync mode), the transmitter transmits the sync character in sync word register 1 followed by the sync character in sync word register 2. the receiver compares the two contiguous sync characters with the program- med sync characters stored in sync word registers 1 and 2. a match implies character synchronization and enables data transfer. the sync pin is used as an output in this mode and is active for the part of the receive clock that detects the sync characters. external sync . in the external sync mode, the transmitter transmits the sync character in sync word register 1. character synchronization for the receiver is established externally. the sync pin is an input that indicates that external character syn- chronization has been achieved. after the sync pat- tern is detected, the external logic must wait for two full receive clock cycles to activate the sync input pin (see figure 11). the sync input pin must be held low until character synchronization is lost. charac- ter assembly begins on the rising edge of the re- ceive clock that precedes the falling edge of the sync input pin. in all cases, after a reset (hardware or software), the receiver is in the hunt phase, during which time the sio looks for character synchronization. the hunt phase can begin only when the receiver is enabled, and data transfer can begin only when character synchronization has been achieved. if character synchronization is lost, the hunt phase can be re-en- tered by setting the enter hunt mode bit in the re- ceiver control register. in the transmit mode, the transmitter always sends the programmed number of sync bits (8 or 16), regardless of the bits per char- acter programmed. in the monosync, bisync, and external sync modes, assembly of received data continues until the sio is reset, or until the receiver is disabled (by command or the dcd pin in the rx auto enables mode), or un- til the cpu sets the enter hunt mode bit. after initial synchronization has been achieved, the operation of the monosync, bisync, and external sync modes is quite similar. any differences are specified in the following text. to set up the sio for synchronous operations, the following registers need to be initialized : mode MK68564 16/46
control register, interrupt control register, recei- ver control register, transmitter control register, sync word 1, and sync word 2. the mode control register must be programmed before other regis- ters to assure proper operation of the sio. the fol- lowing registers are used to transfer data or communicate status between the sio and the cpu or other bus master : command register, status register 0, status register 1, data register, and the vector register. the sio provides four i/o lines in synchronous modes that may be used for modem control, for ex- ternal interrupts, or as general purpose i/o. the re- quest to send ( rts) and data terminal ready ( dtr) pins are outputs that follow the inverted state of their respective bits in the transmit control re- gister. the data carrier detect ( dcd) and clear to send ( cts) pins are inputs that can be used as auto enables to the receiver and transmitter, respective- ly. if external/status interrupts are enabled, the dcd and cts pins will be monitored for a change of status. if these inputs change for a period of time greater than the minimum specified pulse width, an interrupt will be generated. in the following discussion, all interrupt modes are assumed enabled. synchronous transmit initialization . byte-oriented transmitter programs are usually initialized with the following parameters : odd-even or no parity, x1 clock mode, 8- or 16-bit sync character(s), crc polynomial, transmit en- ables, interrupt modes, and transmit character length. if parity is enabled, the transmitter will only add a parity bit to a character that is loaded into the transmit buffer ; it will not add a parity bit to the auto- matically inserted sync character(s) or the crc characters. one of two polynomials may be used with synchro- nous modes, crc-16 (x 16 + x 15 + x 2 + 1) or sdlc- crc (x 16 + x 12 + x 5 + 1). for either polynomial (sdlc mode not selected), the crc generator and checker are reset to all zeros. both the receiver and transmitter use the same polynomial. after reset (hardware or software), or when the transmitter is not enabled, the transmit data (txd) output pin is held high (marking). under program control, the send break bit in the transmitter control register can be set to a one, forcing the txd output pin to a low level (spacing), even if the transmitter is not enabled. the spacing condition will persist un- til the send break bit is reset to a zero. a program- med break is effective as soon as it is written into the transmit control register ; any characters in the transmit buffer and transmit shift register are lost. if the transmit buffer is empty when the transmit en- able bit is set to a one, the transmitter will start sen- ding 8- or 16-bit sync characters. continuous syncs will be transmitted on the txd output pin, as long as no data is loaded into the transmit buffer. note, if a figure 10 : synchronous formats. v000383 MK68564 17/46
character is loaded into the transmit buffer before enabling the transmitter, that character will be sent in place of the sync character(s). start of transmission . transmission will begin with the loading of the first data character into the transmit buffer, if the transmitter is already enabled. for crc to be calculated correctly on each mes- sage, the crc generator must be reset to all zeros before the first data character is loaded into the transmit buffer. this is accomplished by issuing a reset tx crc generator command in the command register. synchronous transmit characteristics . in all synchronous modes, characters are sent with the least-significant bits first. all data is shifted out of the transmit data pin ( txd) on the falling edge of the transmit clock ( txc). the transmitter can transmit from one to eight data bits per character. this re- quires right-hand justification of data written to the transmit buffer, if the selected word length is less than eight bits per character. when the programmed character length is six or seven bits, the unused bits in the transmit buffer are ignored. if a word length of five bits per character or less is selected, the data loaded into the transmit buffer must be formatted as described in the transmit control register part of the register description section. the number of bits per character to be transmitted can be changed on the fly. any data written to the transmit buffer, after the bits per character field is changed, are affected by the change. the same is true of any characters in the buffer at the time the bits per character field is changed. the change in the number of bits per character does not affect the character in the process of being shifted out. a transmitted message can be terminated by crc and sync characters, by sync characters only, or by pad characters (replacing the sync character(s) in the sync word registers with pad characters). how a message is terminated is controlled by the tx un- derrun/eom latch in status register 0. figure 11a : external sync timing. figure 11b : simple external sync delay. v000384 v000385 MK68564 18/46
data transfer . a transmit interrupt is generated each time the transmit buffer becomes empty. the interrupt may be satisfied either by writing another character into the transmit buffer or by resetting the transmit interrupt pending latch with a reset tx in- terrupt pending command. if the interrupt is satisfied with this command, and nothing more is written into the transmit buffer, there can be no further transmit interrupts due to a buffer empty condition, because it is the process of the buffer becoming empty that causes the interrupts. this situation does cause a transmit underrun condition when the data in the shift register is shifted out. another way of detecting when the transmitter re- quires service is to poll the tx buffer empty bit in sta- tus register 0. this bit is set to a one every time the data in the transmit buffer is downloaded into the transmit shift register. when data is written to the transmit buffer, this bit is reset to zero. the sio has all the signals and controls necessary to implement a dma transfer routine for the trans- mitter. the routine may be configured to enable the dma controller, after the first character is written to the transmit buffer, and then using the txrdy out- put pin to signal the dma that the transmitter re- quires service. if a data character is not loaded into the transmit buffer by the time the transmit shift re- gister is empty, the sio enters the transmit under- run condition. transmit underrun/end of message . when the transmitter has no further data to transmit, the sio inserts filler characters to maintain synchronization. the sio has two programmable options for handling this situation : sync characters can be inserted, or the crc characters generated so far can be sent, followed by sync characters. these options are con- trolled by the state of the transmit underrun/eom latch in status register 0. following a hardware or software reset, the trans- mit underrun/eom latch is set to a one. this allows sync characters to be inserted when there is no data to send. crc is not calculated on the automatically inserted sync characters. to allow crc characters to be sent when the transmitter has no data, the transmit underrun/eom latch must be re- set to zero. this latch is reset by issuing a reset tx underrun/eom latch command in the command register. following the crc characters, the sio sends sync characters to terminate the message. there is no restriction as to when, in the message, the transmit underrun/eom latch can be reset, but once the reset command is issued, the 16-bit crc is sent and followed by sync characters the first time the transmitter has no data to send. a transmit un- derrun condition will cause an external/status inter- rupt to be generated whenever the transmit under- run/eom latch is set. for sync character insertion only, at the termination of a message, a transmit interrupt is generated only after the first automatically inserted sync character is loaded into the transmit shift register. the status bits in status register 0 indicate that the transmit underrun/eom latch and the tx buffer empty bit are set. for crc insertion, followed by sync characters, at the termination of a message, the transmit under- run/eom latch is set, and the tx buffer empty bit is reset while the crc characters are being sent. when the crc characters are completely transmit- ted, the tx buffer empty status bit is set, and a transmit interrupt is generated, indicating to the cpu that another message can begin. this trans- mit interrupt occurs when the first sync character following the crc characters is loaded into the transmit shift register. if no more messages are to be transmitted, the program can terminate transmis- sion by disabling the transmitter. crc generation . setting the tx crc enable bit in the transmit control register initiates crc accu- mulation when the program sends the first data character to the sio. to ensure crc is calculated correctly on each message, the reset tx crc gen- erator command should be issued before the first data character of the message is sent to the sio. the tx crc e nable bit can be changed on the fly at any point in the message to include or exclude a particular data character from crc accumulation. the tx crc enable bit should be in the desired state when the data character is loaded from the transmit data buffer into the transmit shift register. to ensure this bit is in the proper state, the tx crc enable bit should be loaded before sending the data character to the sio. transmit termination . the sio is equipped with a special termination feature that maintains data inte- grity and validity. if the transmitter is disabled (by re- setting the transmit enable bit or using the tx auto enable signal) while a data or sync character is being transmitted, the character is transmitted as u- sual but is followed by a marking line instead of sync or crc characters. when the transmitter is disa- bled, a character in the transmit buffer remains in the buffer. if the transmitter is disabled while crc char- acters are being transmitted, the 16-bit transmission is completed, but the remaining bits of the crc characters are replaced by sync characters. MK68564 19/46
bisync protocol transmission . in a bisync proto- col operation, once synchronization is achieved be- tween the transmitter and receiver, fill characters are inserted to maintain that synchronization when the transmitter has no more data to send. the diffe- rent options available in the sio are described in the transmit underrun/end of message part of this sec- tion. if pad characters are to be sent in place of sync characters following the transmission of the crc, the program can set the sio transmitter to eight bits per character and then load "ffh" to the transmit buffer while the crc characters are being sent. al- ternatively, the sync characters in sync word regis- ters 1 and 2 can be redefined to be pad characters during this time. the following example is included to clarify this point : the sio interrupts the cpu with a transmit interrupt when the tx buffer empty bit is set. the cpu recognizes that the last character (etx) of the message has already been sent to the sio transmit buffer by examining the internal program status. to force the sio to send crc, the cpu issues the reset tx underrun/eom latch command and clears the current transmit interrupt with the reset tx interrupt pending command. resetting the inter- rupt with this command prevents the sio from re- questing more data. the sio then begins to send crc (because the transmitter is in an underrun condition) and sets the transmit underrun/eom latch, which causes an external/status interrupt. the cpu satisfies the external/status interrupt by loading pad characters into the transmit buffer and clears the interrupt by issuing the reset exter- nal/status interrupt command. the pad character will follow the crc characters in this sequence, instead of the usual sync characters. a transmit interrupt is generated when the pad character is loaded into the transmit shift register. from this point on, the cpu can send more pad characters or sync characters. the transparent mode of operation in bisync proto- col is made possible with the sio's ability to change the tx crc enable bit at any time during program sequencing and with the additional capability of in- serting 16-bit sync characters. exclusion of dle (data link escape) characters from crc calcula- tion can be achieved by disabling crc calculations immediately preceding the dle character transfer to the transmit buffer. in the case of a transmit un- derrun condition in the transparent mode, a pair of dle-syn characters is sent. the sio can be pro- grammed to send the dle-sync sequence by loa- ding a dle character into sync word register 1 and a sync character into sync word register 2. the sio always transmits two sync characters (16 bits) in bisync mode. if additional sync characters are to be transmitted before a message, the cpu can delay loading data to the transmit buffer until the required number of syncs have been sent. no crc calculations are done on any automatically inserted sync characters. an alternate method of sending additional sync characters is to load the sync char- acters into the transmit buffer, in which case the transmitter will treat the characters as data. the tx crc enable bit should not be set, until true data is going to be loaded into the buffer, to avoid perfor- ming crc calculations on the additional sync char- acters. synchronous receive initialization . byte-oriented receive programs are usually initialized with the following parameters : odd-even or no parity, x1 clock mode (necessary be- cause of the start bit detection logic), 8- or 16-bit sync character(s), crc polynomial, receiver en- ables, interrupt modes, and receive character length. care must be taken if parity is enabled. the receiver will usually detect a parity error on all sync characters, after synchronization is achieved, and on the crc characters. receiver hunt mode . after the sio is initialized for a synchronous receive operation, the receiver is in the hunt phase. during the hunt phase, the receiver does a bit-by-bit comparison of the incoming data stream and the sync character(s) stored in the sync word register 2 (for monosync mode) and sync word registers 1 and 2 (for bisync mode). when a match occurs, the hunt phase is terminated, and the following data bits are assembled into the program- med character length and loaded into the receive data fifo. receive characteristics . the receiver may be pro- grammed to assemble five to eight data bits into a character. the character is right-justified in the shift register and transferred to the receive data fifo. all data transfers to the fifo are in 8-bit groups. when the programmed character length is less than eight bits, the most significant bit(s) transferred with a character will be the least significant bit(s) of the next character. the programmed character length may be changed on the fly during a message ; however, care must be taken to assure that the change is ef- fective before the number of bits specified for the character length have been assembled. when the sync character load inhibit bit in the re- ceiver control register is set, all characters in the MK68564 20/46
receive data stream that match the byte loaded into sync word register 1 will be inhibited from loading into the receive data fifo. the comparison be- tween sync word register 1 and the incoming data occurs at a character boundary time. this is an 8-bit comparison, regardless of the bits per character pro- grammed. crc calculations will be performed on all bytes, even if the characters are not transferred to the receive data fifo, as long as the rx crc en- able bit is set. data transfer and status monitiring . after char- acter synchronization is achieved, the assembled characters are transferred to the receive data fifo, and the status information for each character is transferred to the receive error fifo. the following four modes are available to transfer the received da- ta and its associated status to the cpu. no receive interrupts enabled . this mode is used either for polling operations or for off-line conditions. when transferring data, using a polling routine, the rx character available bit in status register 0 should be checked to determine if a receive charac- ter is available for transfer. only when a character is available should the receive buffer and status re- gister 1 be read. the rx character available bit is set when a character is loaded to the top of the re- ceive data fifo. this bit is reset during a read of the receive buffer. interrupt on first character only . this interrupt mode is normally used to start a dma transfer rou- tine or, in some cases, a polling loop. the sio will generate an interrupt the first time a character is shif- ted to the top of the receive data fifo after this mode is selected or reinitialized. an interrupt will be generated thereafter only if a special receive condition is detected. this mode is reinitialized with the enable interrupt on next receive character command. parity errors do not cause interrupts in this mode ; however, a receive overrun error will. interrupt on every character . this interrupt mode will generate a receiver interrupt every time a char- acter is shifted to the top of the receive data fifo. a special receive condition interrupt on a parity er- ror is optional in this mode. special receive condition interrupt . the special condition interrupt mode is not an interrupt mode as such, but works in conjunction with interrupt on e- very character or interrupt on first character only modes. when the status affects vector bit in either channel is set, a special receive condition will mo- dify the receive interrupt vector to signal the cpu of the special condition. receive overrun error and parity error are the only special receive conditions in synchronous receive mode. the overrun and pa- rity error status bits in status register 1 are latched when they occur ; they will remain latched until an error reset command is issued. as long as either one of these bits is set, a special receive condition interrupt will be generated at every character avai- lable time. since these two status bits are latched, the error status in status register 1, when read, will reflect an error in the current word in the receive buff- er, in addition to any parity or overrun errors recei- ved since the last error reset command. crc error checking and receiver message ter- mination . a crc error check on the received message can be performed on a per character basis under program control. the rx crc en- able bit must set/reset by the program before the next character is transferred from the receive shift register to the receive data fifo. this ensures proper inclusion or exclusion of data characters in the crc check. there is an 8-bit delay between the time a character is transferred to the receive data fifo and the time the same character starts to enter the crc checker. an additional 8-bit times are needed to perform crc calculations on the character. due to this serial na- ture of crc calculations, the receive clock ( rxc) must cycle 16 times after the second crc character has been loaded into the receive data fifo or 20 times (the previous 16 plus 3-bit buffer delay and 1-bit input delay) after the last bit is at the rxd input, before crc calculation is complete. the crc framing error bit in status register 1 will contain the comparison results of the crc checker. the comparison results should be zero, indicating error-free transmission. the results in the status bit are valid only at the end of crc cal- culation. if the result is examined before this time, it usually indicates an error (the bit is high). the comparison is made at each character available time and is valid until the character is read from the receive data fifo. sdlc/hdlc operation introduction the MK68564 sio is capable of handling both high- level synchronous data link control (hdlc) and ibm synchronous data link control (sdlc) proto- cols. in the following discussion, only sdlc is ref- erenced because of the high degree of similarity between sdlc and hdlc. the sdlc mode is considerably different from monosync and bisync protocols, because it is bit o- riented rather than character oriented. bit orienta- tion makes sdlc a flexible protocol in terms of mes- MK68564 21/46
figure 12 : transmit/receive sdlc/hdlc message format. sage length and bit patterns. the sio has several built-in features to handle variable message length. detailed information concerning sdlc protocol can be found in literature on this subject, such as ibm do- cument ga27-3093. the sdlc message, called the frame (figure 12), is opened and closed by flags, which are similar to the sync characters used in other synchronous proto- cols. the sio handles the transmission and reco- gnition of the flag characters that mark the beginning and end of the frame. note that the sio can receive shared-zero flags but cannot transmit them. the 8- bit address field of a sdlc frame contains the se- condary station address. the sio receiver has an address search mode, which recognizes the se- condary station so that it can accept or reject a frame. the control field of the sdlc frame is transparent to the sio ; it is simply transferred to the cpu. the sio handles the frame check sequence in a man- ner that simplifies the program by incorporating fea- tures such as initializing the crc generator to all ones, resetting the crc checker when the opening flag is detected in the receive mode, and sending the frame check/flag sequence in the transmit mode. controller hardware is simplified by automatic zero insertion and deletion logic, contained in the sio. to set up the sio for sdlc operation, the following registers need to be initialized : mode control re- gister, interrupt control register, receiver control register, transmitter control register, sync word register 1, and sync word register 2. the mode control register must be programmed before the o- ther registers to assure proper operation of the sio. the following registers are used to transfer data or communicate status between the sio and the cpu or other bus master when operating in sdlc mode : command register, status register 0, status re- gister 1, data register, and the vector register. sync word register 1 contains the secondary sta- tion address, and sync word register 2 stores the flag character and must be programmed to "01111110". the sio provides four i/o lines in sdlc mode that may be used for modem control, for external inter- rupts, or as general purpose i/o. the request to send (rts) and data terminal ready (dtr) pins are outputs that follow the inverted state of their res- pective bits in the transmit control register. the data carrier detect (dcd) and clear to send (cts) pins are inputs that can be used as auto en- ables to the receiver and transmitter, respectively. if external/status interrupts are enabled, the dcd and cts pins will be monitored for a change of sta- tus. if these inputs change for a period of time grea- ter than the minimum specified pulse width, an in- terrupt will be generated. in the following discussion, all interrupt modes are assumed enabled. sdlc transmit initialization . the sio is initialized for sdlc mode by selecting these parameters in the mode control register : x1 clock mode, sdlc mode, and sync modes enabled. parity is normally not used in sdlc mode, because the transmitter will not add parity to the flag character or the crc characters, thus cau- sing parity errors in the receiver. if crc is to be cal- culated on the transmitted data, the sdlc-crc polynomial must be selected in the interrupt control register (crc-16 polynomial in sdlc mode will produce unknown results). after reset (hardware or software), or when the transmitter is not enabled, the transmit data (txd) output pin is held high (marking). under program control, the send break bit in the transmit control register can be set to a one, forcing the txd output to a low level (spacing), even if the transmitter is not enabled. the spacing condition will persist until the send break bit is reset to a zero. if the transmit buffer is empty when the transmit enable bit is set to a one, the transmitter will start sending flag charac- ters. continuous flags will be transmitted on the txd v000386 MK68564 22/46
output pin as long as no data is loaded into the trans- mit buffer. note : if a character is loaded into the transmit buf- fer before enabling the transmitter, that character will be sent in place of a flag. an abort sequence may be transmitted at any time by issuing the send abort command (command 1). this causes at least eight, but less than fourteen, ones to be sent before the output reverts back to continuous flags. it is possible that the abort se- quence (eight 1's) could follow up to five continuous ones (allowed by the zero insertion logic) and, thus, cause as many as thirteen ones to be sent. any data being transmitted and any data in the transmit buffer is lost when an abort is issued. the zero insertion logic in the transmitter will auto- matically insert a 0 after five continuous ones in the data stream. this does not apply to flags or aborts. start of transmission . transmission will begin with the loading of the first character into the transmit buffer if the transmitter is already enabled. for crc to be calculated correctly on each frame, the crc generator must be initialized to all ones before the first character is loaded. this is accomplished by is- suing a reset tx crc g enerator command in the command register. the first non-flag character transmitted is the address field. the sio does not automatically transmit a station address, this is left to the programmer. the sio will only transmit flags and crc characters automatically. sdlc transmit characteristics . any length sdlc frame can be transmitted. all characters are trans- mitted with the least-significant bits first. all data is shifted out of the transmit data pin (txd) on the fal- ling edge of the transmit clock (txc). the transmit- ter transmit from one to eight data bits per character. this requires right-hand justification of data written to the transmit buffer, if the word length selected is less than eight bits per character. when the pro- grammed character length is six or seven bits, the unused bits in the transmit buffer are ignored. if a word length of five bits per character or less is se- lected, the data loaded into the transmit buffer must be formatted as described in the transmit control register part of the register description section. the number of bits per character to be transmitted can be changed on the fly. any data, written to the transmit buffer after the bits per character field is changed, are affected by the change. the same is true of any characters in the buffer at the time the bits per character field is changed. the change in the number of bits per character does not affect the character in the process of being shifted out. flag characters are always eigth bits in length, and crc is always 16 bits in length, regardless of the pro- grammed bits per character. a transmitted frame can be terminated by crc and a flag, by a flag only, or by an abort. this is controlled by the tx under- run/eom latch and the send abort command. data transfers . a transmit interrupt is generated each time the transmit buffer becomes empty. the interrupt may be satisfied either by writing another character into the transmit buffer or by resetting the transmit interrupt pending latch with a reset tx in- terrupt pending command. if the interrupt is satisfied with this command, and nothing more is written into the transmit buffer, there are no further transmitter interrupts, and a transmit underrun condition will occur when the data in the shift register is shifted out. when another character is written to the buffer and loaded into the shift register, the transmit buffer can again become empty and interrupt the cpu. following the flags in an sdlc operation, the 8-bit address field, control field, and information field may be sent to the sio, using the transmit interrupt mode. the sio transmits the frame check sequence using the transmit underrun feature. when the transmitter is first enabled, the transmit buffer is already empty and obviously cannot then become empty. therefore, no transmit interrupt can occur until after the first data character is written to the transmit buffer. another way of detecting when the transmitter re- quires service is to poll the tx buffer empty bit in sta- tus register 0. this bit is set to a one every time the data in the transmit buffer is downloaded into the transmit shift register. when data is written to the transmit buffer, this bit is reset to zero. the sio has all the signals and controls necessary to implement a dma transfer routine for the trans- mitter. the routine may be configured to enable the dma controller, after the first character is written into the transmit buffer, using the txrdy output pin to signal the dma that the transmitter requires service. the dma transfer can be terminated, when the dma block count is reached, using the tx underrun/eom interrupt. transmit underrun/end of message . sdlc-like protocols do not have provisions for fill characters within a message. the sio, therefore, automatically terminates an sdlc frame when the transmit data buffer is empty, and the output shift register has no MK68564 23/46
more bits to send. it does this by first sending the two bytes of crc and the following these with one or more flags. this technique allows very high-speed transmission under dma or cpu control, without re- quiring the cpu to respond quickly to the end of message situation. the action that the sio takes in the underrun situa- tion depends on the state of the transmit under- run/eom status bit in status register 0. following a reset, the transmit underrun/eom bit is set to a one and prevents the insertion of crc characters during the time there is no data to send. consequently, flag characters are sent. if the transmit underrun/eom status bit is zero when the underrun condition oc- curs, the 16-bit crc character is sent, followed by one or more flag characters. the transmit under- run/eom bit is reset to zero by issuing the reset tx underrun/eom latch command in the command register. the sio begins to send a frame when data is written into the transmit buffer. between the time the first data byte is written and the end of the message, the reset tx underrun/eom latch command must be issued. the transmit underrun/eom status bit will then be in the reset state at the end of the message (when underrun occurs), and crc characters will automatically be sent. the transmission of the first crc bit set the transmit underrun/eom status bit to a one and generates an external/status interrupt. also, while crc is being sent, the tx buffer empty bit in status register 0 is reset to indicate that the transmit shift register is full of crc data. when crc has been completely sent, the tx buffer empty sta- tus bit is set, and a transmit interrupt is generated to indicate that another message may begin. this in- terrupt occurs because crc has been sent, and a flag has been loaded into the shift register. if no more messages are to be sent, the program can ter- minate transmission by disabling the transmitter. although there is no restriction as to when the trans- mit underrun/eom bit can be reset within a mes- sage, it is usually reset after the first data character (secondary address field) is sent to the sio. by re- setting the status bit early in the message, the cpu has additional time (16 bits of crc) to recognize if an unintentional transmit underrun situation has oc- cured and to respond with an abort command. is- suing the abort command stops the flags from going on the line prematurely and eliminates the possibility of the receiver accepting the frame as valid data. this situation can happen if, at the receiving end, the data pattern immediately preceding the automatic flag insertion matches the crc checker, giving a false crc check result. crc generation . the crc generator must be re- set to all ones at the beginning of each frame before crc accumulation can begin. actual accumulation begins on the first data character (address field) loa- ded into the transmit buffer. the tx crc enable bit in the transmit control register should be set to a one before the first character is loaded into the trans- mit buffer. in sdlc mode, all characters between the opening and the closing flags are included in crc accumulation. the output of te crc generator is inverted before it is transmitted. transmit termination . the normal sequence at the end of a frame is a transmit interrupt occurs when the last data char- acter written to the transmit buffer is downloaded in- to the transmit shift register. this interrupt may be cleared by issuing a reset tx interrupt pending command. an external/status interrupt occurs when the first bit of the crc character is transmitted. this interrupt condition should first be tested to see if the interrupt was caused by the tx underrun/eom bit going high and then reset by issuing a reset external/status in- terrupts command. a transmit interrupt occurs when the first bit of the flag is transmitted. this interrupt may be cleared by issuing a reset tx interrupt pending command, by loading the first character of the next message, or by disabling the transmitter. if the transmitter is disabled while a character is being sent, that character (data or flag) is sent in the normal fashion but is followed by a marking line ra- ther than crc or more flag characters. if crc char- acters are being sent at the time the transmitter is disabled, all 16 bits will be transmitted, followed by a marking line ; however, flags are sent in place of crc. a character in the buffer when the transmitter is disabled remains in the buffer. sdlc receive initialization . the receiver is enabled only after all of the receive parameters are initialized. after the receiver enable bit in the receiver control register is set to a one, the receiver will be in the hunt phase and will remain in this phase until the first flag is re- ceived. while in the sdlc mode, the receiver never re-enters the hunt phase, unless specifically in- structed to do so by the program or when an abort character is detected in the incoming data stream. MK68564 24/46
receiver characteristics . the receiver may be programmed to assemble five to eight data bits into a character. the character is right-justified in the shift register and transferred to the receive data fi- fo. all data transfers to the fifo are in 8-bit groups. when the character length programmed is less than eight bits, the most significant bit(s) transferred with a character, will be the least-significant bit(s) of the next character. the character length programmed may be changed on the fly during the reception of a frame ; however, care must be taken to assure that the change is effective, before the number of bits specified for the character length has been assem- bled. the address field in the sdlc frame is defined as an 8-bit field. when the address search mode is se- lected, the receiver will compare the 8-bit character following the flag (first non-flag character) against the address programmed in sync word register 1 or the hardwired global address (11111111). when the address field of the sdlc frame matches either address, data transfer will begin with the address character being loaded into the receive data fifo. if the frame address does not match either address, the receiver will remain idle and continue checking every frame received for an address match. the ad- dress comparison is always done on the first eight bits following a flag, regardless of the bits per char- acter programmed. the sio receiver is capable of matching only one address character. once a match occurs, all data is transferred to the receive data fifo at the program- med bits per character rate. if sdlc extended ad- dress field recognition is used (two or more address characters), the cpu program must be capable of determining whether or not the frame has a correct address field. if the correct address field is not recei- ved, the hunt bit can be set to suspend reception and start searching for the next frame. the control field of an sdlc frame is transparent to the sio ; it is transferred to the data fifo as a data character. all extra zeros, inserted in the data stream by the transmitter, are automatically deleted in the recei- ver. data transfer and status monitoring. after re- ceipt of a valid flag, the assembled characters are transferred to the receive data fifo, and the status information for each character is transferred to the receive error fifo. the following four modes are available to transfer the received data and its asso- ciated status to the cpu. no receiver interrupts enabled . this mode is u- sed for polling operations or for off-line conditions. when transferring data, using a polling routine, the rx character available bit in status register 0 should be checked to determine whether or not a re- ceive character is available for transfer. only when a character is available should the receive buffer and status register 1 be read. the rx character available bit is set to a one every time a character is shifted to the top of the receive data fifo. this bit is reset when the receive buffer is read. interrupt on first character only . this interrupt mode is normally used to start a dma transfer rou- tine, or in some cases, a polling loop. the sio will generate an interrupt the first time a character is shif- ted to the top of the receive data fifo after this mode is selected or reinitialized. an interrupt will be generated thereafter only if a special receive condition is detected. this mode is reinitialized with the enable interrupt on next received character command. parity errors do not cause interrupts in this mode, but a receive overrun error or an end of frame condition will. interrupt on every character . this interrupt mode will generate a receiver interrupt every time a char- acter is shifted to the top of the receive data fifo. a special receive condition interrupt on a parity er- ror is optional in this mode. special receive condition interrupt . the special condition interrupt mode is not an interrupt mode, as such, but works in conjunction with interrupt on e- very character or interrupt on first character only modes. when the status affects vector bit in either channel is set, a special receive condition will mo- dify the receive interrupt vector to signal the cpu of the special condition. receive overrun error, pa- rity error, and end of frame are the special receive conditions in sdlc mode. the overrun and parity error status bits in status register 1 are latched when they occur ; the end of frame bit is not lat- ched. the two bits that are latched will remain lat- ched and will generate a special receive condition interrupt at every character available time until an error reset command is issued. since the two sta- tus bits are latched, the error status in status regis- ter 1, when read, will reflect an error in the current word in the receive buffer, in addition to any parity or overrun errors received since the last error reset command. sdlc receive crc checking . control of the re- ceiver crc checker is automatic. it is reset by the leading flag, and crc is calculated up to the final flag. the byte that has the end of frame bit set is the byte that contains the result of the crc check. if the crc/framing error bit is not set (zero), the crc indicates a valid received message. a special check sequence is used for the sdlc check, be- MK68564 25/46
cause the transmitted crc character is inverted. the final check must be 0001110100001111. he 2- byte crc check characters should be read and dis- carded by the cpu, because the last two bits of the 2-byte sdlc crc check characters are not trans- ferred to the receive data fifo due to the internal timing associated with detecting the closing flag. unlike synchronous modes, the logic path in sdlc mode does not have an 8-bit delay between the time a character is transferred to the receive data fifo and the time a character enters the crc checker. this delay is not needed, because in sdlc, all char- acters between the opening and closing flags are in- cluded in the crc calculations. when the second crc character (six bits only) is loaded into the re- ceive buffer, crc calculation is complete. sdlc receive termination . an sdlc frame is ter- minated when the closing flag is detected. the de- tection of the flag sets the end of frame bit in status register 1 and generates a special receive condi- tion interrupt. in addition to the end of frame bit being set and the results of the crc check, status register 1 has three bits of residue code valid at this time. the residue bits indicate the boundary between the crc check bits and the i-field bits in the frame. a detailed description of the residue code bits is given in the register description section, un- der status register 1. any frame can be prematurely aborted by an abort sequence. aborts are detected if seven or more continuous ones occur in the received data stream. this condition will cause an external/status inter- rupt to be generated with the break/abort bit in sta- tus register 0 set. after the reset external/status interrupts command has been issued, a second in- terrupt will occur when the continuous ones condi- tion has been cleared. this second interrupt can be used to distinguish between the abort and idle line conditions. register description the following sections describe the MK68564 sio registers. each register is detailed in terms of bit configuration, the active states of each bit, their de- finitions, their functions, and their effects upon the internal hardware and external pins. command register (cmdreg) this register contains command and reset functions d7 d6 d5 d4 d3 d2 d1 d0 crc 1 crc 0 cmd 2 cmd 1 cmd 0 loop mode d7, d6 : reset codes 1 and 0 crc 1 crc 0 0 0 1 1 0 1 0 1 null code (no effect) reset receiver crc checker reset transmit crc generator reset tx underrun/end of message latch null code. the null code has no effect on the MK68564 sio. it is used when writing to the command register for some reason other than a crc reset. reset receiver crc checker. it is necessary in synchronous modes (except sdlc) to reset the re- ceiver crc circuitry between received messages. the crc circuitry may be reset by one of the follo- wing : disabling the receiver, setting the enter hunt mode bit in the receiver control register, or issuing this reset command. the crc circuitry is reset automatically in sdlc mode when the end of frame flag is detected. this reset command will ini- tialize the crc checker circuit to all ones in sdlc mode and all zeros in the other synchronous modes. reset transmit crc generator . this command resets the crc generator to all ones in sdlc mode and all zeros in the other synchronous modes. this command should be issued after the transmitter is enabled but before the first character of a message is loaded in the transmit buffer. reset transmit underrun/eom latch . this command resets the underrun/eom latch in status register 0 if the transmitter is enabled. the under- run/eom latch controls the transmission of crc at the end of a message in synchronous modes. when a transmit underrun occurs and this latch is low, crc will be appended to the end of the transmis- sion. used in the programming of the sio. this register is reset to "00h" by a channel or hardware reset. all bits, except loop mode, will be read as zeros during a read cycle. MK68564 26/46
command 0 (null). the null command has no ef- fect on the MK68564 sio. command 1 (send abort). this command is used in sdlc mode to transmit a sequence of eight to thirteen ones. this command always empties the transmit buffer ans sets the tx underrun/eom latch in status register 0 to a one command 2 (reset external/status interrupts) . af- ter an external/status interrupt (a change on a mo- dem line or a break condition, for example), the up- per five bits in status register 0 are latched. this command reenables these bits and allows interrupts to occur again as a result of a status change. lat- ching the status bits captures short pulses, until the cpu has time to read the change. this command should be issued prior to enabling external/status interrupts. command 3 (channel reset). this command di- sables both the receiver and transmitter, forces txd to a marking state ("1"), forces the modem control signals high, resets any pending interrupts from this channel, and resets all control registers. see the re- set section in the sio system interface description for a more detailed list. all control registers for the channel must be rewritten after a channel reset command. command 4 (enable interrupt on next rx charac- ter ). this command is used to reactivate the receive interrupt on first character only interrupt mode. this command is normally issued after the present message is completed but before the next message has started to be assembled. the next character to enter the receive data fifo after this command is issued will cause a receiver interrupt request. note : if the data fifo has more than one character stored when this command is issued, the first pre- viously stored character will cause the receiver in- terrupt request. d5, d4, d3 : command codes command cmd2 cmd1 cmd0 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 null command (no effect) send abort (sdlc mode) reset external/ status interrupts channel reset enable interrupt on next rx character reset tx interrupt pending error reset null command (no effect) d7 d6 d5 d4 d3 d2 d1 d0 clock rate 1 clock rate 0 sync mode 1 sync mode 0 stop bits 1 stop bits 0 parity e/o parity on/off command 5 (reset tx interrupt pending ). when the transmit interrupt enable mode is selected, the transmitter requests an interrupt when the transmit buffer becomes empty. in those cases, where there are no more characters to be sent (at the end of message, for example), issuing this command re- sets the pending transmit interrupt and prevents any further transmitter interrupt requests until the next character has been loaded into the transmit buffer or until crc has b een completely sent. command 6 (error reset). this command resets the upper seven bits in status register 1. anytime a special receive condition exists when receive interrupt on first character only mode is selected, the data with the special condition is held in the re- ceive data fifo until this command is issued. command 7 (null). the null command has no ef- fect on the MK68564 sio. d2, d1 : not used (read as zeros) d0 : loop mode when this bit is set to a 1, the transmitter output is connected to the receiver input and txc is connec- ted to the receiver clock. rxc and rxd pins are not used by the receiver ; they are bypassed internally. rxc may still be used as the baud rate generator output in loop mode. mode control register (modectl) the mode control register contains control bits that affect both the receiver and the transmitter. this re- gister must be initialized before loading the interrupt, tx, and rx control registers, and the sync word registers. this register is reset to "00h" by a chan- nel or hardware reset. d7, d6 : clock rate 1 and 0 these bits specify the multiplier between the input shift clock rates ( txc x rxc) and data rate. the same multiplier is used for both the transmitter and receiver, although the input clock rates may be dif- ferent. in x16, x32, and x64 clock modes, the recei- ver start bit detection logic is enabled ; therefore, for synchronous modes, the x1 clock rate must be specified. any clock rate may be specified for asyn- chronous mode ; however, if the x1 clock rate is se- lected, synchronization between the receive data and the receive clock must be accomplished exter- nally. MK68564 27/46
d5, d4 : sync modes 1 and 0 these bits select the various options for character synchronization. these bits are ignored, unless sync modes is selected in the stop bits filed of this register. d3, d2 : stop bits 1 and 0 these bits determine the number of stop bits added to each asynchronous character that is transmitted. the receiver always checks for one stop bit in asyn- chronous mode. a special code (00) signifies that a synchronous mode is to be selected. 1 1/2 stop bits is not allowed if x1 clock rate is selected, because it will lock up the transmitter. d1 : parity even/odd if the parity enable bit is set, this bit determines whe- ther parity is checked as even or as odd. (1 = even, 0 = odd). this bit is ignored if the parity enable bit is reset. d0 : parity enable if this bit is set to a one, one additional bit position beyond those specified in the bits/character control field is added to the transmitted data and is expected in the receive data. the received parity bit is trans- ferred to the cpu as part of the data character, un- less eight bits per character is selected in the recei- ver control register. interrupt control register (intctl) this register contains the control bits for the various interrupt modes and the dma handshaking signals. this register is reset to "00h" by a channel or hard- ware reset. d7 : crc-16/sdlc-crc this bit selects the crc polynomial used by both the transmitter and receiver. when set to a one, the crc-16 polynomial (x16 + x15 + x2 + 1) is used ; when reset to a zero, the sdlc-crc polynomial (x16 + x12 + x5 + 1) is used. if the sdlc mode is selected, the crc generator and checker are preset to all ones and a special check sequence is used. the sdlc-crc polynomial must be selected in sdlc mode. failure to do so will result in receiver crc errors. when a synchronous mode, other than sdlc, is selected, the crc generator and checker are preset to all zeros (for both polynomials). this bit must be programmed before crc is enabled in the receiver and transmitter control registers, to assure valid crc generation and checking. this bit is igno- red in asynchronous modes. d6 : tx ready enable when this bit is set to a one, the txrdy output pin will pulse low for three clock cycles (clk) when the transmit buffer becomes empty. when this bit is ze- ro, the txrdy pin is held high. d5 : rx ready enable when this bit is set to a one, the txrdy output pin will pulse low for three clockcycles (clk) when a character is available in the receive buffer. if a spe- cial receive condition is detected when the re- ceive interrupt on first character only interrupt mode is selected, the rxrdy pin will not become active ; instead, a special receive condition inter- rupt will be generated. when this bit is zero, the rxrdy pin will be held high sync mode 1 sync mode 0 0 0 1 1 0 1 0 1 8-bit programmed sync 16-bit programmed sync sdlc mode (01111110 flag pattern) external sync mode stop bit 1 stop bit 0 0 0 1 1 0 1 0 1 sync modes 1 stop bit per character 11/2 stop bits per character 2 stop bits per character d7 d6 d5 d4 d3 d2 d1 d0 crc16/ sdlc ctx rdy enable rx rdy enable rx int mode 1 rx int mode 0 status affects tx int enable ext int enable clock rate 1 clock rate 0 multiple 0 0 1 1 0 1 0 1 x1 x16 x32 x64 clock rate = data rate clock rate = 16 x data rate clock rate = 32 x data rate clock rate = 64 x data rate MK68564 28/46
d4, d3 : receive interrupt modes 1 and 0 together, these two bits specify the various charac- ter-avalaible conditions that will cause interrupt re- quests. when receiver interrupts are enabled, a special receive condition can cause an interrupt request and modify the interrupt vector. special re- ceive conditions are : rx overrun error, framing er- ror (in async mode), end of frame (in sdlc mode), and parity error (when selected). the rx overrun error and the parity error conditions are latched in status register 1 when they occur ; they are cleared by an error reset command (command 4) or by a hardware or channel rest. receive interrupts disabled . this mode prevents the receiver from generating an interrupt request and clears any pending receiver interrupts. if a char- acter is avalaible in the receiver data fifo, or if a special receive condition exists before or during the time receiver interrupts are disabled, and recei- ver interrupts are then enabled without clearing these conditions, an interrupt request will immedi- ately be generated. receive interrupt on first character only . the receiver requests an interrupt in this mode on the first available character (or stored fifo character), or on a special receive condition. if a special re- ceive condition occurs, the data with the special condition is held in the receive data fifo until an er- ror reset command (command 6) is issued. the receive interrupt on first character only mode can be re-enabled by the enable interrupt on next rx character command (command 4). if this inter- rupt mode was terminated by a special receive condition, the error reset command must be is- sued, before command 4, for proper operation to re- sume. interrupt on all receive characters . this mode ammows an interrupt for every character received (or character in the receive data fifo) and provides a unique vector (if status affects ector is enabled) when a special receive condition exists. when the interrupt request is due to a special condition, the data containing that condition, the data containing data fifo. d2 : status affects vector when this bit is zero, the value programmed into the vector register is returned during a read cycle or an interrupt acknowledge cycle. if the vector register has not been programmed following a hardware re- set, then "0fh" is returned. when this bit is a one, the vector returned during a read cycle or an interrupt acknowledge cycle is va- riable. the variable field returned depends on the hi- ghest-priority pending interrupt at the start of the cy- cle. the status affects vector control bits from both channels are logical "or" ed together ; therefore, if ei- ther is programmed to a one, its operation affects both channels. this is the only control bit that func- tions in this manner on the MK68564. d1 : transmit interrupt enable when this bit is set to a one, the transmitter will re- quest an interrupt whenever the transmit buffer be- comes empty. when this bit is zero, no transmitter interrupts will be requested. rx int mode 1 rx int mode 0 0 0 1 1 0 1 0 1 receive interrupts disabled receive interrupt on first character only interrupt on all receive characters-parity error is a special receive condition interrupt on all receive characters-parity error is not a special receive condition v2 v1 0 interrupt condition 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ch b transmit buffer empty ch b external/status change ch b receive character available ch b special receive condition* ch a transmit buffer empty ch a external/status change ch a receive character available ch a special receive condition* * special receive conditions : parity error, rx overrun er- d0 : external/status interrupt enable when this bit is set to a one, an interrupt will be re- quested by the external/status logic on any of the fol- lowing occurrences : a transition (high-to-low or low- to-high) on the dcd, cts, or sync input pins, a break/abort condition that has been detected and MK68564 29/46
terminated, or at the beginning of crc transmission when the transmit underrun/eom latch in status register 0 becomes set. when this bit is zero, no ex- ternal/status interrupts will occur. if this bit is set when an external/status condition is pending, an interrupt will be requested. it is re- commended that a reset external/status interrupts command (command 2 in the command register) be issued prior to enabling external/status inter- rupts. sync word register 1 (sync 1) this register is programmed to contain the transmit sync character in the monosync mode, the first eight bits of the 16-bit sync character in the bysinc mode, or the transmit sync character in the external sync mode. this register is not used in asynchronous mode. in the sdlc mode, this register is program- med to contain the secondary address field used to compare against the address field of the sdlc frame. the sio does not automatically transmit the station address at the beginning of a response frame. this register is reset to "00h" by a channel or hardware reset. sync word register 2 (sync 2) this register is programmed to contain the receive sync character in the monosync mode, the last eight bits of the 16-bit sync character in the bisync mode, or a flag character (01111110) in the sdlc mode. this register is not used in the external sync mode and the asynchronous mode. this register is reset to "00h" by a channel or hardware reset. receiver control register (rcvctl) this register contains the control bits and parame- ters for the receiver logic. this register is reset to "00h" by a channel or hardware reset. d7, d6 : receiver bits/character 1 and 0 the state of these two bits determines the number of bits to be assembled as a character in the recei- ved serial data stream. if parity is enabled, one ad- ditional bit will be added to each character. the num- ber of bits per character can be changed while a character is being assembled but only before the number of bits currently programmed is reached. all data is right-justified in the shift register and trans- ferred to the receive data fifo in 8-bit groups. in asynchronous mode, transfers are made at char- acter boundaries, and all unused bits of character are set to a one. in synchronous modes and sdlc mode, an 8-bit segment of the serial data stream is transferred to the data fifo when the internal coun- ter reaches the number of bits per character pro- grammed. for less than eight bits per character, no parity, the msb bit(s) of the first transfer will be the lsb bit(s) of the next transfer. d5 : receiver auto enables when this bit is set to a one, and the receiver ena- ble bit is also set, a low on the dcd input pin be- comes the enable for the receiver. when this bit is zero, the dcd pin is simply an input to the sio, and its status is displayed in status register 0. d4 : enter hunt mode this bit, when written to a one, rearms the receiver synchronization logic and forces the comparison of the received bit stream to the ontents of sync word register 1 and/or sync word register 2, depending upon which synchronous mode is selected, until bit synchronization is achieved. the sio automatically enters the hunt mode after a channel or hardware reset, after an abort condition is detected, or when the receiver is disabled. when the hunt mode is en- tered, the hunt/sync bit in status register 0 is set to a one. when synchronization is achieved, the hunt/sync bit is reset to a zero. if external/status in- terrupts are enabled, an interrupt request will be ge- nerated on both transitions of the hunt/sync bit. en- ter hunt mode has no affect in asynchronous modes. this bit is not latched and will always be read as a zero. d7 d6 d5 d4 d3 d2 d1 d0 sync/ sdlc7 sync/ sdlc6 sync/ sdlc5 sync/ sdlc4 sync/ sdlc3 sync/ sdlc2 sync/ sdlc1 sync/ sdlc0 d7 d6 d5 d4 d3 d2 d1 d0 sync/ sdlc 15 sync/ sdlc 14 sync/ sdlc 13 sync/ sdlc 12 sync/ sdlc 11 sync/ sdlc 10 sync/ sdlc 9 sync/ sdlc 8 rx bits char 1 rx bits char 0 bits/character (no parity) bits/character (parity) 0 0 1 1 0 1 0 1 5 6 7 8 6 7 8 9 d7 d6 d5 d4 d3 d2 d1 d0 rx bits char 1 rx bits char 0 rx auto enab. hunt mode rx crc enab. addr. search strip sync rx enable MK68564 30/46
d3 : receiver crc enable this bit, when set to a one in a synchronous mode other than sdlc, is used to initiate crc calculation at the beginning of the last byte transferred from the receiver shift register to the receive data fifo. this operation occurs independently of the number of bytes in the receive data fifo. as long as this bit is set, crc will be calculated on all characters recei- ved (data or sync). when a particular byte is to be excluded from crc calculation, this bit should be re- set to a zero before the next byte is transferred to the receive data fifo. if this feature is used, care- must be taken to ensure that eight bits per character are selected in the reciever because of an inherent eight-bit delay from the receiver shift register to the crc checker. when this bit is set to a one in sdlc mode, the sio will calculate crc on all bits between the opening and closing flags. there is no delay from the receiver shift register to the crc checker in sdlc mode. this bit is ignored in asynchronous modes. d2 : address search mode setting this bit to a one in sdlc mode forces the comparison of the first non-flag character of a frame with the address programmed in sync word regis- ter 1 or the global address (11111111). if a match does not occur, the frame is ignored, and the recei- ver remains idle until the next frame is detected. no receiver interrupts can occur in this mode, unless there is an address match. this bit is ignored in all modes except sdlc. d1 : sync character load inhibit when this bit is set to a one in any synchronous mode except sdlc, the sio compares the byte in sync word register 1 with the byte about to be loa- ded into the receiver data fifo. if the two bytes are equal, the load is inhibited, and no receiver interrupt will be generated by this character. crc calculation is performed on all bytes, whether they are loaded into the data fifo or not, when the receiver crc is enabled. note that the register used in the compa- rison contains the transmit sync character in mono- sync and external sync modes. this bit is ignored in sdlc mode because all flag characters are auto- matically striped in this mode without performing crc calculations on them. if this bit is set to a one in asynchronous modes, any character received matching the contents of sync word register 1 will not be loaded into the receive data fifo, and no receiver interrupt will be genera- ted for the character. d0 : receiver enable when this bit is set to a one, receiver operation be- gins if rx auto enables mode is not selected. this bit should be set only after all receiver parameters are established, and the receiver is completely ini- tialized. when this bit is zero, the receiver is disabled ; the receiver crc checker is reset, and the receiver is in the hunt mode. transmitter control register (xmtctl) this register contains the control bits and parame- ters for the transmitter logic. this register is reset to "00h" by a channel or hardware reset. d7, d6 transmit bits/character 1 and 0 the state of these two bits determine the number of bits in each byte transferred from the transmit buffer to the transmit shift register. all data written to the transmit buffer must be right-justified with the least- significant bits first. the five or less mode allows transmission of one to five bits per character ; how- ever, the cpu should format the data characters as shown. if parity is enabled, one additional bit per character will be transmitted. d7 d6 d5 d4 d3 d2 d1 d0 tx bits char 1 tx bits char 0 tx auto enables send break tx crc enable dtr rts tx enable tx bits/ char 1 tx bits/ char 0 bits/character (no parity) 0 0 1 1 0 1 0 1 five or less 6 7 8 d7 d6 d5 d4 d3 d2 d1 d0 five or less 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 d 0 0 0 d d 0 0 d d d 0 d d d d d d d d d sends one data bit sends two data bits sends three data bits sends four data bits sends five data bits MK68564 31/46
d5 : transmit auto enables when this bit is set to a one, and the transmit ena- ble bit is also set, a low on the cts input pin will en- able the transmitter. when this bit is zero, the cts pin is simply an input to the sio, and its status is dis- played in status register 0. d4 : send break when set to a one, this bit immediately forces the transmit data output pin (txd) to a spacing condi- tion (continuous 0's), regardless of any data being transmitted at the time. this bit functions, whether the transmitter is enabled or not. when this bit is re- set to zero, the transmitter will continue to send the contents of the transmit shift register. the shift re- gister may contain sync characters, data characters, or all ones. d3 : transmitter crc enable this bit determines if crc calculations are perfor- med on a transmitted data character. if this bit is a one at the time a character is loaded from the trans- mit buffer to the transmit shift register, crc is cal- culated on the character. crc is not calculated on any automatically inserted sync characters. crc is not automatically appended to the end of a message unless this bit is set, and the transmit under- run/eom status bit in status register 0 is reset when a transmit underrun condition occurs. if this bit is a zero when a character is loaded from the transmit buffer into the transmit shift register, no crc calcu- lations are performed on the character. this bit is i- gnored in asynchronous modes. d2 : data terminal ready (dtr) this is the control bit for the dtr output pin. when this bit is set to a one, the dtr pin goes low : when this bit is reset to a zero, the dtr pin goes high. d1 : request to send (rts) this is the control bit for the rts output pin. in syn- chronous modes, when this bit is set to a one, the rts pin goes low ; when this bit is reset to a zero, the rts pin goes high. in asynchronous modes, when this bit is set, the rts pin goes low ; when this bit is reset, the rts pin will go high only after all the bits of the character are transmitted, and the transmit buffer is empty. d0 : transmitter enable data is not transmitted until this bit is set to a one, until the send break bit is reset and, if tx auto en- ables mode is selected, until the cts pin is low. to transmit sync or flag characters in synchronous modes, this bit has to be set when the transmit buffer is empty. data or sync characters in the process of being transmitted are completely sent if this bit is re- set to zero after transmission has started. if this bit is reset during the transmission of a crc character, sync or flag characters are sent instead of the crc character. status register 0 (stat 0) read only this register contains the status of the receive and transmit buffers and the status bits for the five sources of external/status interrupts. d7 : break/abort this bit is reset by a channel or hardware reset. in asynchronous modes, this bit is set when a break sequence (null character plus framing error) is de- tected in the received data stream. an external/sta- tus interrupt, if enabled, is generated when break is detected. the interrupt service routine must issue a reset external/status interrupt command (command 2) to the sio, so the break detection lo- gic can recognize the termination of the break se- quence. the break/abort bit is reset to a zero when the ter- mination of the break sequence is detected in the in- coming data stream. the termination of the break sequence also causes the generation of an exter- nal/status interrupt. command 2 must be issued to enable the break detection logic to look for the next break sequence. a single extraneous null character is present in the receiver after the termination of a break ; it should be read and discarded. in sdlc mode, this bit is set by the detection of an abort sequence (seven or more ones) in the recei- ved data stream. the external/status interrupt is handled the same way as in the case of a break se- quence. the break/abort bit is not used in the other synchronous modes. d6 : transit underrun/eom this bit is set to a one following a hardware or chan- nel reset, when the transmitter is disabled or when a send abort command (command 1) is issued. this bit can only be reset by the reset transmit un- derrun/eom latch command in the command re- gister. this bit is used to control the transmission of d7 d6 d5 d4 d3 d2 d1 d0 break/ abort underrun /eom cts hunt/ sync dcd tx bufr empty interpt pending rx char avail MK68564 32/46
crc at the end of a message in synchronous modes. when a transmit underrun condition occurs and this bit is low. crc will be appended to the end of the transmission, and this bit will be set. only the 0-to-1 transition of this bit causes an external/status interrupt, when enabled. this bit is not used in asyn- chronous modes. d5 : clear to send (cts) this bit indicates the inverted state of the cts input pin at the time of the last change of any of the five external/status bits. any transition of the cts input causes the cts bit to be latched and generates an external/status interrupt request, if enabled. to read the current state of the cts pin, this bit must be read immediately following a reset external/sta- tus interrupts command (command 2). d4 : hunt/sync in asynchronous modes, this bit indicates the inver- ted state of the sync input pin at the time of the last change of any of the five external/status bits. any transition of the sync input causes the hunt/sync bit to be latched and generates an external/status interrupt request, if enabled. to read the current state of the sync pin, this bit must be read imme- diately following a reset external/status interrupt command (command 2). in external sync mode, the sync pin is used by ex- ternal logic to signal character synchronization is a- chieved, the sync pin is driven low on the second rising edge of the receive clock (rxc) on which the last bit of the sync character was received. once the sync pin is low, it should be held low until the end of the message and the driven back high. both transitions on the sync pin cause external/status interrupt requests, if enabled. the inverted state of the sync pin is indicated by this bit. in monosync, bisync, and sdlc modes, this bit in- dicates when the receiver is in the hunt mode. this bit is set to a one following a hardware ir channel re- set, after the enter hunt mode bit is written high, when the receiver is disabled, or when an abort se- quence (sdlc mode) is detected. this bit will re- main in this state until character synchronization is achieved. external/status interrupt requests will be generated on both transitions of the hunt/sync bit. d3 : data carrier detect (dcd) this bit indicates the inverted state of the dcd input pin at the time of the last change of any of the five external/status bits. any transition of the dcd input causes the dcd bit to be latched and generates an external/status interrupt request, if ena-bled. to read the current state of the dcd pin, this bit must be read immediately following a reset external/sta- tus interrupts command (command 2). d2 : transmit buffer empty this bit is set to a one, when the transmit buffer be- comes empty, and when the last crc bit is trans- mitted in synchronous or sdlc modes. this bit is reset when the transmit buffer is loaded or while the crc character is being sent in synchronous or sdlc modes. this bit is set to a one following a hardware or channel reset. d1 : interrupt pending any interrupt condition, pending in the interrupt control logic for this channel, will set this bit to a one. this bit is reset to zero by a hardware channel reset, or when all the interrupt conditions are cleared. d0 : receive character available this bit is set to a one when a character becomes available in the receive data fifo. this bit is reset to zero when the receive data fifo (receive buffer) is read, or by a hardware or channel reset. status register 1 (stat 1) read only this register contains the special receive condition status bits and the residue codes for the i-field in the sdlc receive mode. the all sent bit is set high, and all other bits are reset to a low by a channel or hard- ware reset. d7 : end of frame (sdlc) this bit is used only in sdlc mode. when set to a one, this bit indicates that a valid closing flag has been received and that the crc/framing error bit and residue codes are valid. if receiver interrupts are enabled, a special receive condition interrupt will also be generated. this bit can be reset by is- suing an error reset command (command 6). this bit is also updated by the first character of the follo- wing frame. this bit is a zero in all modes except for d7 d6 d5 d4 d3 d2 d1 d0 end of frame crc/ frame error rx over- run err parity error residue code 2 residue code 1 residue code 0 all sent MK68564 33/46
sdlc. d6 : crc/framing error in asynchronous modes, if a framing error occurs, this bit is set to a one for the receive character in which the framing error occurred. when this bit is set to a one, a special receive condition interrupt will be requested, if receiver interrupts are enabled. detection of a framing error adds an additional one- half bit time to the character time, so that the fra- ming error is not interpreted as a new start bit. in synchronous and sdlc modes, this bit indicates the result of comparing the received crc value to the appropriate check value. a zero indicates that a match has occurred. this bit is usually set since most bit combinations result in a non-zero crc, ex- cept for a correctly completed message. receiver interrupts are not requested by the crc error bit. the crc/framing bit is not latched in any receiver mode. it is always updated when the next character is received. an error reset command (command 6) will always reset this bit to zero. d5 : receive overrun error this bit indicates that the receive data fifo has o- verflowed. only the character that has been written over is flagged with this error. when the character is read, the error condition is latched until reset by the error reset command (command 6). if receiver interrupts are enabled, the overrun character and all subsequent characters received, until the error re- set command is issued, will generate a special re- ceive condition interrupt request. d4 : parity error when parity is enabled, this bit is set to a one for those characters whose parity does not match the programmed sense (even/odd). this bit is latched so that once an error occurs, it remains set until the error reset command (command 6) is issued. if pa- rity is a special receive condition, a parity is a spe- cial receive condition, a parity error will cause a special receive condition interrupt request on the character containing the error and on all subsequent characters until the error reset command is issued. d3, d2, d1 : residue codes 2, 1, and 0 in those cases of the sdlc receive mode, where the i-field is not an integral multiple of the character length, these three bits indicate the length of the re- sidual i-field read in the previous bytes. these codes are meaningful only for the transfer in which the end of frame bit is set. this field is set to 000 by a chan- nel or hardware reset and can leave this state only if sdlc mode is selected, and a character is recei- ved. for eight bits per character if a receive character length, different from eight bits, is used for the i-field, a table similar to the previous one may be constructed for each different character length. for no residue (that is, the last character boundary coincides with the boundary of the i-field and crc field), the residue codes are as follows : d0 : all sent this bit is only active in asynchronous modes ; it is always high in synchronous or sdlc modes. this bit is low while the transmitter is sending characters : it will go high only after all the bits of the character are transmitted, and the transmit buffer is empty. data register (datarg) the data register is actually two separate regis- ters ; a write only register that is the transmit buffer, and a read only register that is the receiver buffer. the receiver buffer is also the top register of a three residue code 2 residue code 1 residue code 0 i-field bits in previous byte i-field bits in second previous byte 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 8 8 bits per character residue code 2 residue code 1 residue code 0 8 bits per character 7 bits per character 6 bits per character 5 bits per character 0 0 0 0 1 0 1 0 1 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 i-fiel bits are right-justified in all cases. MK68564 34/46
register stack called the receive data fifo. the da- ta register is not affected by a channel or hardware reset. time constant register (tcreg) this register contains the time constant used by the down counter in the baud rate generator. the time constant may be changed at any time, but the new value does not take effect until the next time the time constant is loaded into the down counter. it is re- commended that the brg be disabled before wri- ting to this register, as no attempt was made to synchronize the loading of a new time constant with the clock used to drive the brg. this register is re- set to "00h" by a channel or hardware reset. baud rate generator control re- gister (brgctl) this register contains the control bits used to pro- gram the baud rate generator and to select the brg output mode. this register is reset to "00h" by a channel or hardware reset. d7, d6, d5, d4 : not used (read as zeros) d3 : receiver clock, internal/external this bit determines the direction of the rxc pin. when this bit is set to a one, the rxc pin is the output of the baud rate generator. if this bit is a zero, the rxc pin is an input, and an external source must supply the receiver clock. the receiver clock is al- ways the signal on the rxc pin, except in loop mode, when the transmitter clock is connected inter- nally to the receiver clock. d2 : transmitter clock, internal/external this bit determines the direction of the txc pin. when this bit is set to a one, the txc pin is the output of the baud rate generator. if this bit is a zero, the txc pin is an input, and an external source must supply the transmitter clock. the transmit clock is al- ways the signal on the txc pin. d1 : divide by 64/4 this bit specifies the minimum brg input clock cy- cles to output clock cycle. this minimum occurs when the time constant register is loaded with a "01h" value. when this bit is set to a one, 64 input clocks are required for every output clock. when this bit is a zero, four input clocks are required for every output clock. d0 : baud rate generator enable this bit controls the operation of the baud rate gene- rator. when this bit is set to a one, the brg will start counting down from the value left in the down coun- ter when this bit was last reset to zero. if the time constant register is loaded while this bit is reset, the new time constant value is loaded immediately into the down counter. the baud rate generator is disa- bled from counting when this bit is reset. interrupt vector register (vectrg) this register is used to hold a vector that is passed to the cpu during an interrupt acknowledge cycle. this register can also be accessed through a read/write cycle. if the status affects vector bit in the interrupt control register is disabled, the value pro- grammed into the vector register will be passed to the cpu during an interrupt acknowledge cycle or a read cycle. if the status affects vector bit in either channel is enabled, the lower three bits of this regis- ter are modified, according to the table listed in the interrupt control register description. with status affects vector on, and no interrupt pending in the sio, the lower three bits will be read as 011. only o n e vector register exists in the sio, but it can be ac- d7 d6 d5 d4 d3 d2 d1 d0 tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 d7 d6 d5 d4 d3 d2 d1 d0 rxc int/ext txc int/ext divide by 64/4 brg enable d7 d6 d5 d4 d3 d2 d1 d0 v7 v6 v5 v4 v3 v2 * v1 * v0 * * variable if status affects vectors is enabled. MK68564 35/46
MK68564 electrical specifications absolute maximum ratings symbol parameter value unit temperature under bias 25 to 100 c storage temperature 65 to 150 c voltage on any pin with respect to ground 3 to 7 v power dissipation 1.5 w stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only functional operation of the device at these or any other condition above those indicated in the operational section s of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliab i- dc electrical characteristics (v cc = 5.0v 5%, t a =0to70 c) symbol parameter min. max. unit. v ih input high voltage ; all inputs v ss + 2.0 v cc v v il input low voltage ; all inputs v ss 0.3 v ss + 0.8 v i ll power supply current ; outputs open 190 ma i in input leakage current (v in = 0 to 5.25) 10 m a i tsi three-state input current dtack , d0-d7, sync , txc , rxc 0MK68564 36/46
ac electrical characteristics (v cc = 5.0 vdc 5%, gnd = 0 vdc, t a = 0 to 70 c) 4.0 mhz 5.0 mhz number parameter min. max. min. max. unit notes 1 clk period 250 1000 200 1000 ns 2 clk width high 105 80 ns 3 clk width low 105 80 ns 4 clk fall time 30 30 ns 5 clk rise time 30 30 ns 6cs low to clk high (setup time) 0 0 ns 1 7 a1-a5 valid to cs low (setup time) 0 0 ns 8 data valid to cs low (write cycle) 0 0 ns 9cs width high 50 50 ns 1 10 dtack low to a1-a5 invalid (hold time) 0 0 ns 11 dtack low to data invalid (write cycle hold time) 00ns 12 cs high to dtack high (delay) 55 50 ns 13 clk high to dtack low 320 295 ns 14 r/w valid to cs low (setup time) 0 0 ns 15 dtack low to r/w invalid (hold time) 0 0 ns 16 clk low to data out 450 450 ns 17 cs high to data out invalid (hold time) 0 0 ns 11 18 cs high to dtack high impedance 105 100 ns 19 dtack low to cs high 0 0 ns 20 data valid to dtack low 70 70 ns 21 iack width high 50 50 ns 1 22 iack low to clk high (setup time) 0 0 ns 1 23 clk low to intr disabled 410 410 ns 2 24 clk low to data out 330 330 ns 2 25 dtack low to iack , iei , high 0 0 ns 26 iack high to dtack high 55 50 ns 27 iack high to dtack high impedence 105 100 ns 28 iack high to data out invalid (hold time) 0 0 ns 29 data valid to dtack low 195 195 ns 2 30 clk low to ieo low 220 220 ns 3 31 iei low to ieo low 140 140 ns 3 32 iei high to ieo high 190 190 ns 4 33 iack high to ieo high 190 190 ns 4 34 iack high to intr low 200 200 ns 5 35 iei low to clk low (setup time) 10 10 ns 36 iei low to intr disabled 425 425 ns 6 37 iei low to data out valid 225 225 ns 6 38 data out valid to dtack low 55 55 ns 6 39 iack high to data out high impedence 120 90 ns MK68564 37/46
ac electrical characteristics (continued) (v cc = 5.0 vdc 5%, gnd = 0 vdc, t a = 0 to 70 c) 4.0 mhz 5.0 mhz number parameter min. max. min. max. unit notes 40 cs high to data out high impedence 120 90 ns 41 cs or iack high to clk low 100 100 ns 7 42 txrdy or rxrdy width low 3 3 clk's 8, 10 43 clk high txrdy or rxrdy low 300 300 ns 44 clk high to txrdy or rxrdy high 300 300 ns iack high to cs low or cs high to iack low (not shown) 50 50 ns 1 45 cts , dcd , sync pulse width high 200 200 ns 46 cts , dcd , sync pulse width low 200 200 ns 47 txc period 1000 dc 800 dc ns 9 48 txc width low 180 dc 180 dc ns 49 txc width high 180 dc 180 dc ns 50 txc low to txd delay (x1 mode) 300 300 ns 51 txc low to intr low delay 5959 clk's 10 52 rxc period 1000 dc 800 dc ns 9 53 rxc width low 180 dc 180 dc ns 54 rxc width high 180 dc 180 dc ns 55 rxd to rxc high setup time (x1 mode) 0 0 ns 56 rxc high to rxd hold time (x1 mode) 140 140 ns 57 rxc high to intr low delay 10 13 10 13 clk's 10 58 rxc high to sync low delay (output modes) 4747 clk's 10 59 reset low 1 1 clk 10 60 xtal 1 width high (ttl in) 100 80 ns 61 xtal 1 width low (ttl in) 100 80 ns 62 xtal 1 period (ttl in) 250 2000 200 2000 ns 63 xtal 1 period (crystal in) 250 1000 200 1000 ns notes : 1. this specification only applies if the sio has completed all operations initiated by the previous bus cycle, w hen cs or iack was asserted. following a read, write, or interrupt acknoledge cycle, all operations are complete within two clk cycles after the rising edge of cs or iack. if cs or iack is asserted prior to the completion of the internal operations, the new bus cycle will be post poned. 2. if iei meets the setup time to the falling edge of clk, 1 1/2 cycles following the clocking in of iack. 3. no internal interrupt request pending at the start of an interrupt acknoledge cycle. 4. time starts when first signal goes invalid (high). 5. if an internal interrupt is pending at the end of the interrupt acknoledge cycle. 6. if note 2 timing is not met. 7. if this spec is met, the delay listed in note 1 will be one clk cycle inst ead of two. 8. ready signals w ill be negated asynchr onous to the clk, if the condition causing the assertion of the signals is cleared. 9. if rxc and txc are asynchronous to the system clock, the maximum clock rate into rxc and txc should be no more than one-fifth the system clock rate. if rxc and txc are synchronized to the falling edge of the system clock, the maximum clock rate into rxc and txc can be one-fourth the system clock rate. 10. system clock. 11. due to the dynamic nature of the internal data bus, if cs is held low for more than a few hundred m illisec onds the MK68564 38/46
figure 15 : read cycle. figure 13 : output test load. figure 14 : intr test load. for all outputs except for dtack, d0-d7 intr, xtal2 c l = 130pf r l = 16k w r 1 = 450 w dtack, d0-d7 c l = 130pf r l = 6k w r 1 = 200 w note : waveform measurement for all inputs and outputs are specified at logic high = 2.0 volts, logic low = 0.8 volts. note : xtal2 output test load is a crystal. MK68564 39/46
figure 16 : write cycle. note : waveform measurements for all inputs and outputs are specified at logic high = 2.0 volts, logic low = 0.8 volts. v000390 MK68564 40/46
figure 17 : interrupt acknoledge cycle ( iei low). note : waveform measurements for all inputs and outputs are specified at logic high = 2.0 volts, logic low = 0.8 volts. v000391 MK68564 41/46
figure 18 : interrupt acknoledge cycle ( iei high). note : waveform measurements for all inputs and outputs are specified at logic high = 2.0 volts, logic low = 0.8 volts. v000392 MK68564 42/46
figure 19 : dma interface timing. note : waveform measurements for all inputs and outputs are specified at logic high = 2.0 volts, logic low = 0.8 volts. v000393 MK68564 43/46
figure 20 : serial interface timing. note : waveform measurements for all inputs and outputs are specified at logic high = 2.0 volts, logic low = 0.8 volts. v000394 MK68564 44/46
MK68564 52-pin plastic leader chip carrier (q) MK68564 45/46
MK68564 48-pin plastic dual-in-line package MK68564 order codes part no. package type max. clock frequency temperature range MK68564n-04 plastic 4.0 mhz 0 to 70 c MK68564n-05 plastic 5.0 mhz 0 to 70 c MK68564q-04 plcc 4.0 mhz 0 to 70 c MK68564q-05 plcc 5.0 mhz 0 to 70 c information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved. purchase of i 2 c components by sgs-thomson microelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. MK68564 46/46

▲Up To Search▲

Price & Availability of MK68564

	To Download MK68564 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .